Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2018 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <baseboard/gpio.h> |
| 17 | #include <baseboard/variants.h> |
| 18 | #include <commonlib/helpers.h> |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 19 | |
praveen hodagatta pranesh | da5491a | 2018-09-28 22:31:49 +0800 | [diff] [blame] | 20 | #if !IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 21 | static const struct pad_config gpio_table[] = { |
| 22 | /* GPPC */ |
| 23 | /* A0 : RCINB_TIME_SYNC_1 */ |
| 24 | /* A1 : ESPI_IO_0 */ |
| 25 | /* A2 : ESPI_IO_1 */ |
| 26 | /* A3 : ESPI_IO_2 */ |
| 27 | /* A4 : ESPI_IO_3 */ |
| 28 | /* A5 : ESPI_CSB */ |
| 29 | /* A6 : SERIRQ */ |
| 30 | /* A7 : PRIQAB_GSP10_CS1B */ |
| 31 | PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE), |
| 32 | /* A8 : CLKRUNB */ |
| 33 | PAD_CFG_GPO(GPP_A8, 1, PLTRST), |
| 34 | /* A9 : CLKOUT_LPC_0_ESPI_CLK */ |
| 35 | /* A10 : CLKOUT_LPC_1 */ |
| 36 | /* A11 : PMEB_GSP11_CS1B */ |
| 37 | PAD_CFG_GPI_SCI_LOW(GPP_A11, UP_20K, DEEP, LEVEL), |
| 38 | /* A12 : BM_BUSYB_ISH__GP_6 */ |
| 39 | /* A13 : SUSWARNB_SUSPWRDNACK */ |
| 40 | PAD_CFG_GPO(GPP_A13, 1, PLTRST), |
| 41 | /* A14 : SUS_STATB_ESPI_RESETB */ |
| 42 | /* A15 : SUSACKB */ |
| 43 | PAD_CFG_GPO(GPP_A15, 1, PLTRST), |
| 44 | /* A16 : SD_1P8_SEL */ |
Maulik V Vaghela | bad8fbb | 2018-08-07 14:48:20 +0530 | [diff] [blame] | 45 | PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST), |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 46 | /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */ |
| 47 | /* A18 : ISH_GP_0 */ |
| 48 | PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1), |
| 49 | /* A19 : ISH_GP_1 */ |
| 50 | PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1), |
Maulik V Vaghela | bad8fbb | 2018-08-07 14:48:20 +0530 | [diff] [blame] | 51 | /* A20 : ISH_GP_2 */ |
| 52 | PAD_CFG_NF(GPP_A20, UP_20K, DEEP, NF1), |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 53 | /* A21 : ISH_GP_3 */ |
| 54 | PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1), |
| 55 | /* A22 : ISH_GP_4 */ |
| 56 | PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1), |
| 57 | /* A23 : ISH_GP_5 */ |
| 58 | PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), |
| 59 | |
| 60 | /* B0 : CORE_VID_0 */ |
| 61 | /* B1 : CORE_VID_1 */ |
| 62 | /* B2 : VRALERTB */ |
| 63 | PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE), |
| 64 | /* B3 : CPU_GP_2 */ |
| 65 | PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE), |
| 66 | /* B4 : CPU_GP_3 */ |
| 67 | PAD_CFG_GPO(GPP_B4, 1, DEEP), |
| 68 | /* B5 : SRCCLKREQB_0 */ |
| 69 | /* B6 : SRCCLKREQB_1 */ |
| 70 | /* B7 : SRCCLKREQB_2 */ |
| 71 | /* B8 : SRCCLKREQB_3 */ |
| 72 | /* B9 : SRCCLKREQB_4 */ |
| 73 | /* B10 : SRCCLKREQB_5 */ |
| 74 | /* B11 : EXT_PWR_GATEB */ |
| 75 | PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), |
| 76 | /* B12 : SLP_S0B */ |
| 77 | /* B13 : PLTRSTB */ |
| 78 | /* B14 : SPKR */ |
| 79 | PAD_CFG_GPO(GPP_B14, 1, PLTRST), |
| 80 | /* B15 : GSPI0_CS0B */ |
| 81 | PAD_CFG_GPO(GPP_B15, 0, DEEP), |
| 82 | /* B16 : GSPI0_CLK */ |
| 83 | PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE), |
| 84 | /* B17 : GSPI0_MISO */ |
| 85 | PAD_CFG_GPO(GPP_B17, 1, PLTRST), |
| 86 | /* B18 : GSPI0_MOSI */ |
| 87 | PAD_CFG_GPO(GPP_B18, 1, PLTRST), |
| 88 | /* B19 : GSPI1_CS0B */ |
| 89 | /* B20 : GSPI1_CLK_NFC_CLK */ |
| 90 | /* B21 : GSPI1_MISO_NFC_CLKREQ */ |
| 91 | /* B22 : GSP1_MOSI */ |
| 92 | /* B23 : SML1ALERTB_PCHHOTB */ |
| 93 | PAD_CFG_GPO(GPP_B23, 1, DEEP), |
| 94 | |
| 95 | /* C0 : SMBCLK */ |
| 96 | /* C1 : SMBDATA */ |
| 97 | /* C2 : SMBALERTB */ |
| 98 | PAD_CFG_GPO(GPP_C2, 1, DEEP), |
| 99 | /* C3 : SML0CLK */ |
| 100 | /* C4 : SML0DATA */ |
| 101 | /* C5 : SML0ALERTB */ |
| 102 | PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL), |
| 103 | /* C6 : SML1CLK */ |
| 104 | /* C7 : SML1DATA */ |
| 105 | /* C8 : UART0_RXD */ |
| 106 | PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT), |
| 107 | /* C9 : UART0_TXD */ |
| 108 | PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE), |
| 109 | /* C10 : UART0_RTSB */ |
| 110 | PAD_CFG_GPO(GPP_C10, 0, PLTRST), |
| 111 | /* C11 : UART0_CTSB */ |
Maulik V Vaghela | bad8fbb | 2018-08-07 14:48:20 +0530 | [diff] [blame] | 112 | PAD_CFG_TERM_GPO(GPP_C11, 1, UP_20K, DEEP), |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 113 | /* C12 : UART1_RXD_ISH_UART1_RXD */ |
| 114 | PAD_CFG_GPO(GPP_C12, 1, PLTRST), |
| 115 | /* C13 : UART1_RXD_ISH_UART1_TXD */ |
| 116 | /* C14 : UART1_RXD_ISH_UART1_RTSB */ |
| 117 | /* C15 : UART1_RXD_ISH_UART1_CTSB */ |
| 118 | PAD_CFG_GPO(GPP_C15, 1, PLTRST), |
| 119 | /* C16 : I2C0_SDA */ |
| 120 | /* C17 : I2C0_SCL */ |
| 121 | /* C18 : I2C1_SDA */ |
| 122 | /* C19 : I2C1_SCL */ |
| 123 | /* C20 : UART2_RXD */ |
| 124 | /* C21 : UART2_TXD */ |
| 125 | /* C22 : UART2_RTSB */ |
| 126 | /* C23 : UART2_CTSB */ |
| 127 | |
| 128 | /* D0 : SPI1_CSB_BK_0 */ |
| 129 | /* D1 : SPI1_CLK_BK_1 */ |
| 130 | /* D2 : SPI1_MISO_IO_1_BK_2 */ |
| 131 | /* D3 : SPI1_MOSI_IO_0_BK_3 */ |
| 132 | /* D4 : IMGCLKOUT_0_BK_4 */ |
| 133 | /* D5 : ISH_I2C0_SDA */ |
| 134 | /* D6 : ISH_I2C0_SCL */ |
| 135 | /* D7 : ISH_I2C1_SDA */ |
| 136 | /* D8 : ISH_I2C1_SCL */ |
| 137 | /* D9 : ISH_SPI_CSB */ |
| 138 | PAD_CFG_GPO(GPP_D9, 1, PLTRST), |
| 139 | /* D10 : ISH_SPI_CLK */ |
Maulik V Vaghela | bad8fbb | 2018-08-07 14:48:20 +0530 | [diff] [blame] | 140 | PAD_CFG_GPI_APIC(GPP_D10, UP_20K, PLTRST, LEVEL, INVERT), |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 141 | /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */ |
| 142 | PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL), |
| 143 | /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */ |
| 144 | /* D13 : ISH_UART0_RXD_SML0BDATA */ |
| 145 | PAD_CFG_GPO(GPP_D13, 1, DEEP), |
| 146 | /* D14 : ISH_UART0_TXD_SML0BCLK */ |
| 147 | PAD_CFG_GPO(GPP_D14, 1, PLTRST), |
| 148 | /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */ |
| 149 | /* D16 : ISH_UART0_CTSB_SML0BALERTB */ |
| 150 | PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL), |
| 151 | /* D17 : DMIC_CLK_1_SNDW3_CLK */ |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 152 | /* D18 : DMIC_DATA_1_SNDW3_DATA */ |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 153 | /* D19 : DMIC_CLK_0_SNDW4_CLK */ |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 154 | /* D20 : DMIC_DATA_0_SNDW4_DATA */ |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 155 | /* D21 : SPI1_IO_2 */ |
| 156 | PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), |
| 157 | /* D22 : SPI1_IO_3 */ |
| 158 | PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), |
| 159 | /* D23 : SPP_MCLK */ |
Maulik V Vaghela | bad8fbb | 2018-08-07 14:48:20 +0530 | [diff] [blame] | 160 | |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 161 | /* E1 : SATAXPCIE_1_SATAGP_1 */ |
| 162 | /* E2 : SATAXPCIE_2_SATAGP_2 */ |
| 163 | PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST), |
| 164 | /* E3 : CPU_GP_0 */ |
| 165 | PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), |
| 166 | /* E4 : SATA_DEVSLP_0 */ |
| 167 | PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), |
| 168 | /* E5 : SATA_DEVSLP_1 */ |
| 169 | /* E6 : SATA_DEVSLP_2 */ |
| 170 | PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE), |
| 171 | /* E7 : CPU_GP_1 */ |
| 172 | PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE), |
| 173 | /* E8 : SATA_LEDB */ |
| 174 | /* E9 : USB2_OCB_0_GP_BSSB_CLK */ |
| 175 | /* E10 : USB2_OCB_1_GP_BSSB_DI */ |
| 176 | /* E11 : USB2_OCB_2 */ |
| 177 | /* E12 : USB2_OCB_3 */ |
| 178 | /* E13 : DDSP_HPD_0_DISP_MISC_0 */ |
| 179 | /* E14 : DDSP_HPD_0_DISP_MISC_1 */ |
| 180 | /* E15 : DDSP_HPD_0_DISP_MISC_2 */ |
| 181 | /* E16 : EMMC_EN */ |
| 182 | PAD_CFG_GPO(GPP_E16, 1, PLTRST), |
| 183 | /* E17 : EDP_HPD_DISP_MISC_4 */ |
| 184 | /* E18 : DDPB_CTRLCLK */ |
| 185 | /* E19 : DDPB_CTRLDATA */ |
| 186 | /* E20 : DDPC_CTRLCLK */ |
| 187 | /* E21 : DDPC_CTRLDATA */ |
| 188 | /* E22 : DDPD_CTRLCLK */ |
| 189 | /* E23 : DDPD_CTRLDATA */ |
| 190 | |
| 191 | /* F0 : CNV_GNSS_PA_BLANKING */ |
| 192 | PAD_CFG_GPI(GPP_F0, NONE, PLTRST), |
| 193 | /* F1 : CNV_GNSS_FAT */ |
| 194 | PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP), |
| 195 | /* F2 : CNV_GNSS_SYSCK */ |
| 196 | PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), |
| 197 | /* F3 : GPP_F_3 */ |
| 198 | PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), |
| 199 | /* F4 : CNV_BRI_DT_UART0_RTSB */ |
| 200 | /* F5 : CNV_BRI_RSP_UART0_RXD */ |
| 201 | /* F6 : CNV_RGI_DT_UART0_TXD */ |
| 202 | /* F7 : CNV_RGI_DT_RSP_UART9_CTSB */ |
| 203 | /* F8 : CNV_MFUART2_RXD */ |
| 204 | PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1), |
| 205 | /* F9 : CNV_MFUART2_TXD */ |
| 206 | PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1), |
| 207 | /* F10 : GPP_F_10 */ |
| 208 | PAD_CFG_GPO(GPP_F10, 1, PLTRST), |
| 209 | /* F11 : EMMC_CMD */ |
| 210 | /* F12 : EMMC_DATA0 */ |
| 211 | /* F13 : EMMC_DATA1 */ |
| 212 | /* F14 : EMMC_DATA2 */ |
| 213 | /* F15 : EMMC_DATA3 */ |
| 214 | /* F16 : EMMC_DATA4 */ |
| 215 | /* F17 : EMMC_DATA5 */ |
| 216 | /* F18 : EMMC_DATA6 */ |
| 217 | /* F19 : EMMC_DATA9 */ |
| 218 | /* F20 : EMMC_RCLK */ |
| 219 | /* F21 : EMMC_CLK */ |
| 220 | /* F22 : EMMC_RESETB */ |
| 221 | /* F23 : BIOS_REC */ |
| 222 | PAD_CFG_GPI(GPP_F23, UP_20K, DEEP), |
| 223 | /* G0 : SD3_D2 */ |
| 224 | /* G1 : SD3_D0_SD4_RCLK_P */ |
| 225 | /* G2 : SD3_D1_SD4_RCLK_N */ |
| 226 | /* G3 : SD3_D2 */ |
| 227 | /* G4 : SD3_D3 */ |
| 228 | /* G5 : SD3_CDB */ |
| 229 | PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1), |
| 230 | /* G6 : SD3_CLK */ |
| 231 | /* G7 : SD3_WP */ |
| 232 | PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), |
| 233 | |
| 234 | /* H0 : SSP2_SCLK */ |
| 235 | /* H1 : SSP2_SFRM */ |
| 236 | /* H2 : SSP2_TXD */ |
| 237 | /* H3 : SSP2_RXD */ |
| 238 | /* H4 : I2C2_SDA */ |
| 239 | /* H5 : I2C2_SCL */ |
| 240 | /* H6 : I2C3_SDA */ |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 241 | /* H7 : I2C3_SCL */ |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 242 | /* H8 : I2C4_SDA */ |
| 243 | /* H9 : I2C4_SCL */ |
| 244 | /* H10 : I2C5_SDA_ISH_I2C2_SDA */ |
| 245 | PAD_CFG_GPO(GPP_H10, 1, PLTRST), |
| 246 | /* H11 : I2C5_SCL_ISH_I2C2_SCL */ |
| 247 | PAD_CFG_GPO(GPP_H11, 1, PLTRST), |
| 248 | /* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */ |
| 249 | PAD_CFG_GPO(GPP_H12, 1, PLTRST), |
| 250 | /* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */ |
| 251 | PAD_CFG_GPO(GPP_H13, 1, PLTRST), |
| 252 | /* H14 : M2_SKT2_CFG_2 */ |
Maulik V Vaghela | bad8fbb | 2018-08-07 14:48:20 +0530 | [diff] [blame] | 253 | PAD_CFG_GPO(GPP_H14, 1, PLTRST), |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 254 | /* H15 : M2_SKT2_CFG_3 */ |
| 255 | PAD_CFG_GPO(GPP_H15, 1, PLTRST), |
| 256 | /* H16 : CAM5_PWR_EN */ |
| 257 | PAD_CFG_GPO(GPP_H16, 1, PLTRST), |
| 258 | /* H17 : CAM5_FLASH_STROBE */ |
| 259 | PAD_CFG_GPO(GPP_H17, 1, PLTRST), |
| 260 | /* H18 : BOOTMPC */ |
| 261 | /* H19 : TIMESYNC_0 */ |
| 262 | PAD_CFG_GPO(GPP_H19, 1, PLTRST), |
| 263 | /* H20 : IMGCLKOUT_1 */ |
| 264 | /* H21 : GPPC_H_21 */ |
| 265 | /* H22 : GPPC_H_22 */ |
Maulik V Vaghela | bad8fbb | 2018-08-07 14:48:20 +0530 | [diff] [blame] | 266 | PAD_CFG_GPI(GPP_H22, NONE, DEEP), |
Lijian Zhao | b7d2a6f | 2018-08-27 11:51:29 -0700 | [diff] [blame] | 267 | #if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP) |
| 268 | PAD_CFG_GPO(GPP_H22, 1, PLTRST), |
| 269 | #else |
| 270 | PAD_CFG_GPI(GPP_H22, NONE, DEEP), |
| 271 | #endif |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 272 | /* H23 : GPPC_H_23 */ |
| 273 | |
| 274 | /* GPD */ |
| 275 | /* GPD_0 : BATLOWB */ |
| 276 | /* GPD_1 : ACPRESENT */ |
| 277 | /* GPD_2 : LAN_WAKEB */ |
| 278 | /* GPD_3 : PWRBTNB */ |
| 279 | /* GPD_4 : SLP_S3B */ |
| 280 | /* GPD_5 : SLP_S4B */ |
| 281 | /* GPD_6 : SLP_AB */ |
| 282 | /* GPD_7 : GPD_7 */ |
| 283 | /* GPD-8 : SUSCLK */ |
| 284 | /* GPD-9 : SLP_WLANB */ |
| 285 | /* GPD-10 : SLP_5B */ |
| 286 | /* GPD_11 : LANPHYPC */ |
| 287 | }; |
| 288 | |
praveen hodagatta pranesh | da5491a | 2018-09-28 22:31:49 +0800 | [diff] [blame] | 289 | #else |
| 290 | static const struct pad_config gpio_table[] = { |
| 291 | /* GPPC */ |
| 292 | /* A0 : RCIN_ESPI_ALERT1 */ |
| 293 | /* A1 : ESPI_IO_0 */ |
| 294 | /* A2 : ESPI_IO_1 */ |
| 295 | /* A3 : ESPI_IO_2 */ |
| 296 | /* A4 : ESPI_IO_3 */ |
| 297 | /* A5 : ESPI_CSB */ |
| 298 | /* A6 : SERIRQ */ |
| 299 | /* A7 : PRIQAB_ESPI_ALERT0 */ |
| 300 | /* A8 : CLKRUNB */ |
| 301 | PAD_CFG_GPO(GPP_A8, 1, PLTRST), |
| 302 | /* A9 : CLKOUT_LPC_0_ESPI_CLK */ |
| 303 | /* A10 : CLKOUT_LPC_1 */ |
| 304 | /* A11 : I2S_CODEC_INT */ |
| 305 | PAD_CFG_GPI_APIC_LOW(GPP_A11, UP_20K, PLTRST), |
| 306 | /* A12 : BM_BUSYB_ISH__GP_6 */ |
| 307 | /* A13 : SUSWARNB_SUSPWRDNACK */ |
| 308 | PAD_CFG_GPO(GPP_A13, 1, PLTRST), |
| 309 | /* A14 : SUS_STATB_ESPI_RESETB */ |
| 310 | /* A15 : SUSACKB */ |
| 311 | PAD_CFG_GPO(GPP_A15, 1, PLTRST), |
| 312 | /* A16 : TCH_PAD_INT_N */ |
| 313 | PAD_CFG_GPI_APIC(GPP_A16, NONE, PLTRST, LEVEL, INVERT), |
| 314 | /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */ |
| 315 | /* A18 : ISH_GP_0 */ |
| 316 | /* A19 : ISH_GP_1 */ |
| 317 | /* A20 : ISH_GP_2 */ |
| 318 | /* A21 : ISH_GP_3 */ |
| 319 | /* A22 : ISH_GP_4 */ |
| 320 | /* A23 : ISH_GP_5 */ |
| 321 | |
| 322 | /* B0 : SPI_TPM_INIT */ |
| 323 | PAD_CFG_GPI_SCI_LOW(GPP_B0, UP_20K, DEEP, EDGE_SINGLE), |
| 324 | /* B1 : GSPI1_CS1 */ |
| 325 | /* B2 : VRALERTB */ |
| 326 | PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE), |
| 327 | /* B3 : BT_RF_KILL */ |
| 328 | PAD_CFG_GPO(GPP_B3, 1, DEEP), |
| 329 | /* B4 : WIFI_RF_KILL */ |
| 330 | PAD_CFG_GPO(GPP_B4, 1, DEEP), |
| 331 | /* B5 : SRCCLKREQB_0 */ |
| 332 | /* B6 : SRCCLKREQB_1 */ |
| 333 | /* B7 : SRCCLKREQB_2 */ |
| 334 | /* B8 : SRCCLKREQB_3 */ |
| 335 | /* B9 : SRCCLKREQB_4 */ |
| 336 | /* B10 : SRCCLKREQB_5 */ |
| 337 | /* B11 : I2S_MCLK */ |
| 338 | /* B12 : SLP_S0B */ |
| 339 | /* B13 : PLTRSTB */ |
| 340 | /* B14 : SPKR */ |
| 341 | PAD_CFG_GPO(GPP_B14, 1, PLTRST), |
| 342 | /* B15 : GSPI0_CS0B */ |
| 343 | PAD_CFG_GPO(GPP_B15, 0, DEEP), |
| 344 | /* B16 : GSPI0_CLK */ |
| 345 | PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE), |
| 346 | /* B17 : GSPI0_MISO */ |
| 347 | PAD_CFG_GPO(GPP_B17, 1, PLTRST), |
| 348 | /* B18 : I2C_TCH_PNL_PWREN */ |
| 349 | PAD_CFG_GPO(GPP_B18, 1, PLTRST), |
| 350 | /* B19 : GSPI1_CS0B */ |
| 351 | /* B20 : GSPI1_CLK */ |
| 352 | /* B21 : GSPI1_MISO */ |
| 353 | /* B22 : GSP1_MOSI */ |
| 354 | /* B23 : EC_SLP_S0_CS_N */ |
| 355 | PAD_CFG_GPO(GPP_B23, 1, PLTRST), |
| 356 | |
| 357 | /* C0 : SMBCLK */ |
| 358 | /* C1 : SMBDATA */ |
| 359 | /* C2 : SMBALERTB */ |
| 360 | PAD_CFG_GPO(GPP_C2, 1, DEEP), |
| 361 | /* C3 : SML0CLK */ |
| 362 | /* C4 : SML0DATA */ |
| 363 | /* C5 : WIFI_WAKE_N */ |
| 364 | PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL), |
| 365 | /* C6 : SML1CLK */ |
| 366 | /* C7 : SML1DATA */ |
| 367 | /* C8 : UART0_RXD */ |
| 368 | PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT), |
| 369 | /* C9 : UART0_TXD */ |
| 370 | PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE), |
| 371 | /* C10 : UART0_RTSB */ |
| 372 | PAD_CFG_GPO(GPP_C10, 0, PLTRST), |
| 373 | /* C11 : UART0_CTSB */ |
| 374 | PAD_CFG_TERM_GPO(GPP_C11, 1, UP_20K, DEEP), |
| 375 | /* C12 : UART1_RXD_ISH_UART1_RXD */ |
| 376 | PAD_CFG_GPO(GPP_C12, 1, PLTRST), |
| 377 | /* C13 : UART1_RXD_ISH_UART1_TXD */ |
| 378 | /* C14 : SSD1_RESET */ |
| 379 | PAD_CFG_GPO(GPP_C14, 1, PLTRST), |
| 380 | /* C15 : SSD2_RESET */ |
| 381 | PAD_CFG_GPO(GPP_C15, 1, PLTRST), |
| 382 | /* C16 : I2C0_SDA */ |
| 383 | /* C17 : I2C0_SCL */ |
| 384 | /* C18 : I2C1_SDA */ |
| 385 | /* C19 : I2C1_SCL */ |
| 386 | /* C20 : UART2_RXD */ |
| 387 | /* C21 : UART2_TXD */ |
| 388 | /* C22 : UART2_RTSB */ |
| 389 | /* C23 : UART2_CTSB */ |
| 390 | |
| 391 | /* D0 : SPI1_CSB_BK_0 */ |
| 392 | /* D1 : SPI1_CLK_BK_1 */ |
| 393 | /* D2 : SPI1_MISO_IO_1_BK_2 */ |
| 394 | /* D3 : SPI1_MOSI_IO_0_BK_3 */ |
| 395 | /* D4 : IMGCLKOUT_0_BK_4 */ |
| 396 | /* D5 : ISH_I2C0_SDA */ |
| 397 | /* D6 : ISH_I2C0_SCL */ |
| 398 | /* D7 : SSP2_RXD */ |
| 399 | PAD_CFG_GPI_INT(GPP_D7, NONE, PLTRST, LEVEL), |
| 400 | /* D8 : SSP2_SCLK */ |
| 401 | PAD_CFG_GPI_INT(GPP_D8, NONE, PLTRST, LEVEL), |
| 402 | /* D9 : ISH_SPI_CSB */ |
| 403 | PAD_CFG_GPO(GPP_D9, 1, PLTRST), |
| 404 | /* D10 : ISH_SPI_CLK */ |
| 405 | PAD_CFG_GPI_APIC(GPP_D10, UP_20K, PLTRST, LEVEL, INVERT), |
| 406 | /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */ |
| 407 | PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL), |
| 408 | /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */ |
| 409 | /* D13 : ISH_UART0_RXD_SML0BDATA */ |
| 410 | PAD_CFG_GPO(GPP_D13, 1, DEEP), |
| 411 | /* D14 : ISH_UART0_TXD_SML0BCLK */ |
| 412 | PAD_CFG_GPO(GPP_D14, 1, PLTRST), |
| 413 | /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */ |
| 414 | /* D16 : ISH_UART0_CTSB_SML0BALERTB */ |
| 415 | PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL), |
| 416 | /* D17 : DMIC_CLK_1_SNDW3_CLK */ |
| 417 | /* D18 : DMIC_DATA_1_SNDW3_DATA */ |
| 418 | /* D19 : DMIC_CLK_0_SNDW4_CLK */ |
| 419 | /* D20 : DMIC_DATA_0_SNDW4_DATA */ |
| 420 | /* D21 : SPI1_IO_2 */ |
| 421 | PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), |
| 422 | /* D22 : SPI1_IO_3 */ |
| 423 | PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), |
| 424 | /* D23 : ISH_I2C2_SCL_I2C3_SCL */ |
| 425 | |
| 426 | /* E0 : SATAXPCIE_0_SATAGP_0 */ |
| 427 | /* E1 : SATAXPCIE_1_SATAGP_1 */ |
| 428 | /* E2 : SATAXPCIE_2_SATAGP_2 */ |
| 429 | PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST), |
| 430 | /* E3 : EC_SMI_N */ |
| 431 | PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), |
| 432 | /* E4 : SATA_DEVSLP_0 */ |
| 433 | PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), |
| 434 | /* E5 : SATA_DEVSLP_1 */ |
| 435 | /* E6 : SATA_DEVSLP_2 */ |
| 436 | PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE), |
| 437 | /* E7 : CPU_GP_1 */ |
| 438 | PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE), |
| 439 | /* E8 : SATA_LEDB */ |
| 440 | /* E9 : USB2_OCB_0 */ |
| 441 | /* E10 : USB2_OCB_1 */ |
| 442 | /* E11 : USB2_OCB_2 */ |
| 443 | /* E12 : USB2_OCB_3 */ |
| 444 | |
| 445 | /* F0 : SATAXPCIE_3_SATAGP_3 */ |
| 446 | /* F1 : SATAXPCIE_4_SATAGP_4 */ |
| 447 | /* F2 : SATAXPCIE_5_SATAGP_5 */ |
| 448 | /* F3 : SATAXPCIE_6_SATAGP_6 */ |
| 449 | /* F4 : SLOT2_RST_N */ |
| 450 | PAD_CFG_GPO(GPP_F4, 1, PLTRST), |
| 451 | /* F5 : SATA_DEVSLP_3 */ |
| 452 | /* F6 : SATA_DEVSLP_4 */ |
| 453 | /* F7 : ME_PG_LED */ |
| 454 | PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, LEVEL), |
| 455 | /* F8 : SATA_DEVSLP_6 */ |
| 456 | /* F9 : PEG_SLOT_RST */ |
| 457 | PAD_CFG_GPO(GPP_F9, 1, PLTRST), |
| 458 | /* F10 : BIOS_RECOVERY */ |
| 459 | PAD_CFG_GPI_INT(GPP_F10, NONE, PLTRST, LEVEL), |
| 460 | /* F11 : SATA_SLOAD */ |
| 461 | /* F12 : SATA_S-DATA_OUT1 */ |
| 462 | /* F13 : SATA_S-DATA_OUT0 */ |
| 463 | /* F14 : PS_ON */ |
| 464 | /* F15 : USB2_OC_4 */ |
| 465 | /* F16 : USB2_OC_5 */ |
| 466 | /* F17 : USB2_OC_6 */ |
| 467 | /* F18 : USB2_OC_7 */ |
| 468 | /* F19 : EDP_VDDEN */ |
| 469 | /* F20 : EDP_BKLTEN */ |
| 470 | /* F21 : EDP_BKLTCTL */ |
| 471 | /* F22 : DDPF_C_TRLCLK */ |
| 472 | /* F23 : DDPF_C_TRLDATA */ |
| 473 | |
| 474 | /* G0 : SD_DATA */ |
| 475 | /* G1 : SD_DATA0 */ |
| 476 | /* G2 : SD_DATA1 */ |
| 477 | /* G3 : SD_DATA2 */ |
| 478 | /* G4 : SD_DATA3 */ |
| 479 | /* G5 : GPP_G_5_SD3_CDB */ |
| 480 | PAD_CFG_NF(GPP_G5, UP_20K, DEEP, GPIO), |
| 481 | /* G6 : SD_CLK */ |
| 482 | /* G7 : GPP_G_7_SD3_WP */ |
| 483 | PAD_CFG_NF(GPP_G7, UP_20K, DEEP, GPIO), |
| 484 | |
| 485 | /* H0 : SRCCLKREQB_6 */ |
| 486 | /* H1 : SRCCLKREQB_7 */ |
| 487 | /* H2 : SRCCLKREQB_8 */ |
| 488 | /* H3 : SRCCLKREQB_9 */ |
| 489 | /* H4 : SRCCLKREQB_10 */ |
| 490 | /* H5 : SRCCLKREQB_11 */ |
| 491 | /* H6 : SRCCLKREQB_12 */ |
| 492 | /* H7 : SRCCLKREQB_13 */ |
| 493 | /* H8 : SRCCLKREQB_14 */ |
| 494 | /* H9 : SRCCLKREQB_15 */ |
| 495 | /* H10 : Audio Power Enable */ |
| 496 | PAD_CFG_GPO(GPP_H10, 1, PLTRST), |
| 497 | /* H11 : SML_2_DATA */ |
| 498 | /* H12 : SML_2_ALERT */ |
| 499 | /* H13 : SML_3_CLK */ |
| 500 | /* H14 : SML_3_DATA */ |
| 501 | /* H15 : SML_3_ALERT */ |
| 502 | /* H16 : TBT_CIO_PWREN */ |
| 503 | PAD_CFG_GPO(GPP_H16, 1, PLTRST), |
| 504 | /* H17 : TBT_FORCE_PWR */ |
| 505 | PAD_CFG_GPO(GPP_H17, 0, PLTRST), |
| 506 | /* H18 : SML_4_ALERT */ |
| 507 | /* H19 : ISH_I2C0_SDA */ |
| 508 | /* H20 : ISH_I2C0_SCL */ |
| 509 | /* H21 : ISH_I2C1_SDA */ |
| 510 | /* H22 : ISH_I2C1_SCL */ |
| 511 | /* H23 : TBT_CIO_PLUG_EVENT_N */ |
| 512 | PAD_CFG_GPI_SCI_LOW(GPP_H23, NONE, PLTRST, EDGE_SINGLE), |
| 513 | |
| 514 | /* I0 : DDPB_HPD_0 */ |
| 515 | /* I1 : DDPC_HPD_1 */ |
| 516 | /* I2 : DPPD_HPD_2 */ |
| 517 | /* I3 : DPPE_HPD_3 */ |
| 518 | /* I4 : EDP_HPD */ |
| 519 | /* I5 : DDPB_C_TRLCLK */ |
| 520 | /* I6 : DDPB_C_TRLDATA */ |
| 521 | /* I7 : DDPC_C_TRLCLK */ |
| 522 | /* I8 : DDPC_C_TRLDATA */ |
| 523 | /* I9 : DDPD_C_TRLCLK */ |
| 524 | /* I10 : DDPD_C_TRLDATA */ |
| 525 | /* I11 : M2_SKT2_C_FG0 */ |
| 526 | /* I12 : M2_SKT2_CFG1 */ |
| 527 | /* I13 : M2_SKT2_C_FG2 */ |
| 528 | /* I14 : M2_SKT2_C_FG3 */ |
| 529 | |
| 530 | /* J0 : I2C_TCH_PNL_INT */ |
| 531 | PAD_CFG_GPI_APIC(GPP_J0, UP_20K, PLTRST, EDGE_SINGLE, INVERT), |
| 532 | /* J1 : CPU_C10_GATE */ |
| 533 | /* J2 : FPS_INT_N */ |
| 534 | PAD_CFG_GPI_APIC(GPP_J2, NONE, PLTRST, EDGE_SINGLE, NONE), |
| 535 | /* J3 : FPS_RST_N */ |
| 536 | PAD_CFG_GPO(GPP_J3, 1, PLTRST), |
| 537 | /* J4 : CNV_BRI_DT_UART0_RTS */ |
| 538 | /* J5 : CNV_BRI_RSP_UART0_RXD */ |
| 539 | /* J6 : CNV_RGI_DT_UART0_TXD */ |
| 540 | /* J7 : CNV_RGI_RSP_UART0_CTS */ |
| 541 | /* J8 : CNV_M_FUART2_RXD */ |
| 542 | /* J9 : CNV_M_FUART2_TXD */ |
| 543 | /* J10 : I2C_TCH_PNL_RST_N */ |
| 544 | PAD_CFG_GPO(GPP_J10, 1, PLTRST), |
| 545 | /* J11 : SPEAKER_PD */ |
| 546 | PAD_CFG_GPO(GPP_J11, 1, PLTRST), |
| 547 | |
| 548 | /* K0 : GPP_K0 */ |
| 549 | /* K1 : SATA_ODD_PWRGT_R */ |
| 550 | PAD_CFG_GPO(GPP_K1, 1, PLTRST), |
| 551 | /* K2 : SATA_ODD_DA_N */ |
| 552 | PAD_CFG_GPI_SCI_HIGH(GPP_K2, NONE, PLTRST, EDGE_SINGLE), |
| 553 | /* K3 : GPP_K3 */ |
| 554 | /* K4 : GPP_K4 */ |
| 555 | /* K5 : GPP_K5 */ |
| 556 | /* K6 : GPP_K6 */ |
| 557 | /* K7 : GPP_K7 */ |
| 558 | /* K8 : GPP_K8 */ |
| 559 | /* K9 : GPP_K9 */ |
| 560 | /* K10 : GPP_K10 */ |
| 561 | /* K11 : RUNTIME_SCI */ |
| 562 | PAD_CFG_GPI_SCI_LOW(GPP_K11, UP_20K, PLTRST, LEVEL), |
| 563 | /* K12 : GSXDOUT */ |
| 564 | /* K13 : GSXSLOAD */ |
| 565 | /* K14 : GSXDIN */ |
| 566 | /* K15 : GSXSRESET */ |
| 567 | /* K16 : GSXCLK */ |
| 568 | /* K17 : ADR_COMPLETE */ |
| 569 | /* K18 : SLOT2_WAKE_N */ |
| 570 | PAD_CFG_GPI_SCI_LOW(GPP_K18, NONE, PLTRST, LEVEL), |
| 571 | /* K19 : SMI */ |
| 572 | /* K20 : GPP_K20 */ |
| 573 | /* K21 : GPP_K21 */ |
| 574 | /* K22 : IMGCLKOUT_0 */ |
| 575 | /* K23 : IMGCLKOUT_1 */ |
| 576 | |
| 577 | /* GPD */ |
| 578 | /* GPD_0 : BATLOWB */ |
| 579 | /* GPD_1 : ACPRESENT */ |
| 580 | /* GPD_2 : LAN_WAKEB */ |
| 581 | /* GPD_3 : PWRBTNB */ |
| 582 | /* GPD_4 : SLP_S3B */ |
| 583 | /* GPD_5 : SLP_S4B */ |
| 584 | /* GPD_6 : SLP_AB */ |
| 585 | /* GPD_7 : GPD_7 */ |
| 586 | /* GPD-8 : SUSCLK */ |
| 587 | /* GPD-9 : SLP_WLANB */ |
| 588 | /* GPD-10 : SLP_5B */ |
| 589 | /* GPD_11 : LANPHYPC */ |
| 590 | }; |
| 591 | #endif |
| 592 | |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 593 | /* Early pad configuration in bootblock */ |
| 594 | static const struct pad_config early_gpio_table[] = { |
| 595 | |
| 596 | |
| 597 | }; |
| 598 | |
| 599 | const struct pad_config *__weak variant_gpio_table(size_t *num) |
| 600 | { |
| 601 | *num = ARRAY_SIZE(gpio_table); |
| 602 | return gpio_table; |
| 603 | } |
| 604 | |
Lijian Zhao | b7d2a6f | 2018-08-27 11:51:29 -0700 | [diff] [blame] | 605 | const struct pad_config *__weak |
| 606 | variant_early_gpio_table(size_t *num) |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 607 | { |
| 608 | *num = ARRAY_SIZE(early_gpio_table); |
| 609 | return early_gpio_table; |
| 610 | } |
| 611 | |
| 612 | static const struct cros_gpio cros_gpios[] = { |
| 613 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 614 | }; |
| 615 | |
Lijian Zhao | b7d2a6f | 2018-08-27 11:51:29 -0700 | [diff] [blame] | 616 | const struct cros_gpio * __weak variant_cros_gpios(size_t *num) |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 617 | { |
| 618 | *num = ARRAY_SIZE(cros_gpios); |
| 619 | return cros_gpios; |
| 620 | } |