Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Google Inc. |
| 6 | * Copyright (C) 2018 Intel Corporation |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Elyes HAOUAS | 6d19a20 | 2018-11-22 11:15:29 +0100 | [diff] [blame] | 18 | #include <arch/acpi.h> |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 19 | DefinitionBlock( |
| 20 | "dsdt.aml", |
| 21 | "DSDT", |
Elyes HAOUAS | 0cca6e2 | 2018-11-13 14:23:29 +0100 | [diff] [blame] | 22 | 0x02, // DSDT revision: ACPI v2.0 and up |
Elyes HAOUAS | 6d19a20 | 2018-11-22 11:15:29 +0100 | [diff] [blame] | 23 | OEM_ID, |
| 24 | ACPI_TABLE_CREATOR, |
Maulik V Vaghela | dfc9917 | 2018-08-07 12:06:23 +0530 | [diff] [blame] | 25 | 0x20110725 // OEM revision |
| 26 | ) |
| 27 | { |
| 28 | // Some generic macros |
| 29 | #include <soc/intel/cannonlake/acpi/platform.asl> |
| 30 | |
| 31 | // global NVS and variables |
| 32 | #include <soc/intel/cannonlake/acpi/globalnvs.asl> |
| 33 | |
| 34 | Scope (\_SB) { |
| 35 | Device (PCI0) |
| 36 | { |
| 37 | #include <soc/intel/cannonlake/acpi/northbridge.asl> |
| 38 | #include <soc/intel/cannonlake/acpi/southbridge.asl> |
| 39 | } |
| 40 | } |
| 41 | |
| 42 | #if IS_ENABLED(CONFIG_CHROMEOS) |
| 43 | // Chrome OS specific |
| 44 | #include <vendorcode/google/chromeos/acpi/chromeos.asl> |
| 45 | #endif |
| 46 | |
| 47 | // Chipset specific sleep states |
| 48 | #include <soc/intel/cannonlake/acpi/sleepstates.asl> |
| 49 | |
| 50 | } |