Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stddef.h> |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 18 | #include <arch/cbfs.h> |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 19 | #include <cpu/x86/mtrr.h> |
| 20 | #include <romstage_handoff.h> |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 21 | #include <soc/gpio.h> |
| 22 | #include <soc/iomap.h> |
| 23 | #include <soc/lpc.h> |
| 24 | #include <soc/pci_devs.h> |
| 25 | #include <soc/romstage.h> |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 26 | #include <soc/baytrail.h> |
Marc Jones | 7868797 | 2015-04-22 23:16:31 -0600 | [diff] [blame] | 27 | #include <drivers/intel/fsp1_0/fsp_util.h> |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 28 | |
| 29 | /** |
| 30 | * /brief mainboard call for setup that needs to be done before fsp init |
| 31 | * |
| 32 | */ |
| 33 | void early_mainboard_romstage_entry() |
| 34 | { |
| 35 | |
| 36 | } |
| 37 | |
| 38 | /** |
| 39 | * Get function disables - most of these will be done automatically |
| 40 | * @param fd_mask |
| 41 | * @param fd2_mask |
| 42 | */ |
| 43 | void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) |
| 44 | { |
| 45 | |
| 46 | } |
| 47 | |
| 48 | /** |
| 49 | * /brief mainboard call for setup that needs to be done after fsp init |
| 50 | * |
| 51 | */ |
| 52 | void late_mainboard_romstage_entry() |
| 53 | { |
| 54 | |
| 55 | } |
| 56 | |
| 57 | const uint32_t mAzaliaVerbTableData13[] = { |
| 58 | /* |
| 59 | *ALC262 Verb Table - 10EC0262 |
| 60 | */ |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 61 | /* Pin Complex (NID 0x11) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 62 | 0x01171CF0, |
| 63 | 0x01171D11, |
| 64 | 0x01171E11, |
| 65 | 0x01171F41, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 66 | /* Pin Complex (NID 0x12) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 67 | 0x01271CF0, |
| 68 | 0x01271D11, |
| 69 | 0x01271E11, |
| 70 | 0x01271F41, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 71 | /* Pin Complex (NID 0x14) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 72 | 0x01471C10, |
| 73 | 0x01471D40, |
| 74 | 0x01471E01, |
| 75 | 0x01471F01, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 76 | /* Pin Complex (NID 0x15) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 77 | 0x01571CF0, |
| 78 | 0x01571D11, |
| 79 | 0x01571E11, |
| 80 | 0x01571F41, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 81 | /* Pin Complex (NID 0x16) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 82 | 0x01671CF0, |
| 83 | 0x01671D11, |
| 84 | 0x01671E11, |
| 85 | 0x01671F41, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 86 | /* Pin Complex (NID 0x18) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 87 | 0x01871C20, |
| 88 | 0x01871D98, |
| 89 | 0x01871EA1, |
| 90 | 0x01871F01, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 91 | /* Pin Complex (NID 0x19) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 92 | 0x01971C21, |
| 93 | 0x01971D98, |
| 94 | 0x01971EA1, |
| 95 | 0x01971F02, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 96 | /* Pin Complex (NID 0x1A) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 97 | 0x01A71C2F, |
| 98 | 0x01A71D30, |
| 99 | 0x01A71E81, |
| 100 | 0x01A71F01, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 101 | /* Pin Complex (NID 0x1B) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 102 | 0x01B71C1F, |
| 103 | 0x01B71D40, |
| 104 | 0x01B71E21, |
| 105 | 0x01B71F02, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 106 | /* Pin Complex (NID 0x1C) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 107 | 0x01C71CF0, |
| 108 | 0x01C71D11, |
| 109 | 0x01C71E11, |
| 110 | 0x01C71F41, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 111 | /* Pin Complex (NID 0x1D) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 112 | 0x01D71C01, |
| 113 | 0x01D71DC6, |
| 114 | 0x01D71E14, |
| 115 | 0x01D71F40, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 116 | /* Pin Complex (NID 0x1E) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 117 | 0x01E71CF0, |
| 118 | 0x01E71D11, |
| 119 | 0x01E71E11, |
| 120 | 0x01E71F41, |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 121 | /* Pin Complex (NID 0x1F) */ |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 122 | 0x01F71CF0, |
| 123 | 0x01F71D11, |
| 124 | 0x01F71E11, |
| 125 | 0x01F71F41 }; |
| 126 | |
| 127 | const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { |
| 128 | /* |
| 129 | * VerbTable: (RealTek ALC262) |
| 130 | * Revision ID = 0xFF, support all steps |
| 131 | * Codec Verb Table For AZALIA |
| 132 | * Codec Address: CAd value (0/1/2) |
| 133 | * Codec Vendor: 0x10EC0262 |
| 134 | */ |
| 135 | { |
| 136 | 0x10EC0262, /* Vendor ID/Device IDA */ |
| 137 | 0x0000, /* SubSystem ID */ |
| 138 | 0xFF, /* Revision IDA */ |
| 139 | 0x01, /* Front panel support (1=yes, 2=no) */ |
| 140 | 0x000B, /* Number of Rear Jacks = 11 */ |
| 141 | 0x0002 /* Number of Front Jacks = 2 */ |
| 142 | }, |
| 143 | (uint32_t *)mAzaliaVerbTableData13 } }; |
| 144 | |
| 145 | const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = { |
| 146 | .Pme = 1, |
| 147 | .DS = 1, |
| 148 | .DA = 0, |
| 149 | .HdmiCodec = 1, |
| 150 | .AzaliaVCi = 1, |
| 151 | .Rsvdbits = 0, |
| 152 | .AzaliaVerbTableNum = 1, |
| 153 | .AzaliaVerbTable = (PCH_AZALIA_VERB_TABLE *)mAzaliaVerbTable, |
| 154 | .ResetWaitTimer = 300 }; |
| 155 | |
| 156 | /** /brief customize fsp parameters here if needed |
| 157 | */ |
| 158 | void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) |
| 159 | { |
| 160 | UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; |
| 161 | |
| 162 | /* Initialize the Azalia Verb Tables to mainboard specific version */ |
| 163 | UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 164 | |
| 165 | /* Disable 2nd DIMM on Bakersport*/ |
Martin Roth | 1010868 | 2016-01-31 10:37:22 -0700 | [diff] [blame] | 166 | #if IS_ENABLED(CONFIG_BOARD_INTEL_BAKERSPORT_FSP) |
Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 167 | UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */ |
| 168 | #endif |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 169 | } |