Lance Zhao | 1eb1e3b | 2016-03-01 17:03:23 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
Martin Roth | ac04781 | 2016-04-11 13:48:21 -0600 | [diff] [blame] | 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Lance Zhao | 1eb1e3b | 2016-03-01 17:03:23 -0800 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <soc/romstage.h> |
| 19 | #include <string.h> |
| 20 | #include <fsp/api.h> |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 21 | #include <fsp/soc_binding.h> |
Lance Zhao | 1eb1e3b | 2016-03-01 17:03:23 -0800 | [diff] [blame] | 22 | |
| 23 | static const uint8_t swizzling_rvp1[] = { |
| 24 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, |
| 25 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, |
| 26 | }; |
| 27 | |
| 28 | static const uint8_t swizzling0_rvp2[] = { |
| 29 | 23, 21, 16, 17, 18, 19, 22, 20, 3, 5, 2, 4, 7, 0, 6, 1, |
| 30 | 24, 27, 26, 30, 28, 25, 29, 31, 13, 8, 12, 15, 10, 14, 11, 9, |
| 31 | }; |
| 32 | |
| 33 | static const uint8_t swizzling1_rvp2[] = { |
| 34 | 10, 14, 12, 13, 9, 11, 15, 8, 1, 6, 2, 5, 0, 7, 3, 4, |
| 35 | 21, 18, 19, 22, 20, 17, 16, 23, 29, 28, 24, 27, 31, 30, 26, 25, |
| 36 | }; |
| 37 | |
| 38 | static const uint8_t swizzling2_rvp2[] = { |
| 39 | 13, 15, 10, 14, 9, 12, 8, 11, 22, 19, 16, 23, 21, 17, 20, 18, |
| 40 | 26, 24, 28, 29, 31, 30, 27, 25, 4, 5, 1, 0, 3, 6, 7, 2, |
| 41 | }; |
| 42 | |
| 43 | static const uint8_t swizzling3_rvp2[] = { |
| 44 | 0, 3, 6, 7, 4, 5, 1, 2, 20, 17, 21, 16, 23, 18, 22, 19, |
| 45 | 15, 9, 11, 14, 12, 8, 13, 10, 26, 29, 24, 31, 25, 30, 27, 28, |
| 46 | }; |
| 47 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 48 | static void rvp1_fill_memory_params(FSPM_UPD *mupd) |
Lance Zhao | 1eb1e3b | 2016-03-01 17:03:23 -0800 | [diff] [blame] | 49 | { |
| 50 | mupd->FspmConfig.Profile = 33; |
| 51 | mupd->FspmConfig.DIMM0SPDAddress = 0xa0; |
| 52 | mupd->FspmConfig.DIMM1SPDAddress = 0xa4; |
| 53 | mupd->FspmConfig.Ch0_RankEnable = 0; |
| 54 | mupd->FspmConfig.Ch0_DeviceWidth = 0; |
| 55 | mupd->FspmConfig.Ch0_DramDensity = 0; |
| 56 | mupd->FspmConfig.Ch0_Option = 3; |
| 57 | mupd->FspmConfig.Ch1_RankEnable = 0; |
| 58 | mupd->FspmConfig.Ch1_DeviceWidth = 0; |
| 59 | mupd->FspmConfig.Ch1_DramDensity = 0; |
| 60 | mupd->FspmConfig.Ch1_Option = 3; |
| 61 | mupd->FspmConfig.Ch2_RankEnable = 0; |
| 62 | mupd->FspmConfig.Ch2_DeviceWidth = 0; |
| 63 | mupd->FspmConfig.Ch2_DramDensity = 0; |
| 64 | mupd->FspmConfig.Ch2_Option = 3; |
| 65 | mupd->FspmConfig.Ch3_RankEnable = 0; |
| 66 | mupd->FspmConfig.Ch3_DeviceWidth = 0; |
| 67 | mupd->FspmConfig.Ch3_DramDensity = 0; |
| 68 | mupd->FspmConfig.Ch3_Option = 3; |
| 69 | memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); |
| 70 | memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); |
| 71 | memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); |
| 72 | memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); |
| 73 | } |
| 74 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 75 | static void rvp2_fill_memory_params(FSPM_UPD *mupd) |
Lance Zhao | 1eb1e3b | 2016-03-01 17:03:23 -0800 | [diff] [blame] | 76 | { |
| 77 | mupd->FspmConfig.Profile = 5; |
| 78 | mupd->FspmConfig.DIMM0SPDAddress = 0; |
| 79 | mupd->FspmConfig.DIMM1SPDAddress = 0; |
| 80 | mupd->FspmConfig.Ch0_RankEnable = 3; |
| 81 | mupd->FspmConfig.Ch0_DeviceWidth = 2; |
| 82 | mupd->FspmConfig.Ch0_DramDensity = 0; |
| 83 | mupd->FspmConfig.Ch0_Option = 3; |
| 84 | mupd->FspmConfig.Ch1_RankEnable = 3; |
| 85 | mupd->FspmConfig.Ch1_DeviceWidth = 2; |
| 86 | mupd->FspmConfig.Ch1_DramDensity = 0; |
| 87 | mupd->FspmConfig.Ch1_Option = 3; |
| 88 | mupd->FspmConfig.Ch2_RankEnable = 3; |
| 89 | mupd->FspmConfig.Ch2_DeviceWidth = 2; |
| 90 | mupd->FspmConfig.Ch2_DramDensity = 0; |
| 91 | mupd->FspmConfig.Ch2_Option = 3; |
| 92 | mupd->FspmConfig.Ch3_RankEnable = 3; |
| 93 | mupd->FspmConfig.Ch3_DeviceWidth = 2; |
| 94 | mupd->FspmConfig.Ch3_DramDensity = 0; |
| 95 | mupd->FspmConfig.Ch3_Option = 3; |
| 96 | memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, swizzling0_rvp2, |
| 97 | sizeof(swizzling0_rvp2)); |
| 98 | memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, swizzling1_rvp2, |
| 99 | sizeof(swizzling1_rvp2)); |
| 100 | memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, swizzling2_rvp2, |
| 101 | sizeof(swizzling2_rvp2)); |
| 102 | memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, swizzling3_rvp2, |
| 103 | sizeof(swizzling3_rvp2)); |
| 104 | } |
| 105 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 106 | void mainboard_memory_init_params(FSPM_UPD *mupd) |
Lance Zhao | 1eb1e3b | 2016-03-01 17:03:23 -0800 | [diff] [blame] | 107 | { |
| 108 | mupd->FspmConfig.Package = 0; |
| 109 | mupd->FspmConfig.MemoryDown = 1; |
| 110 | mupd->FspmConfig.DDR3LPageSize = 0; |
| 111 | mupd->FspmConfig.DDR3LASR = 0; |
| 112 | mupd->FspmConfig.ScramblerSupport = 1; |
| 113 | mupd->FspmConfig.ChannelHashMask = 0; |
| 114 | mupd->FspmConfig.SliceHashMask = 0; |
| 115 | mupd->FspmConfig.InterleavedMode = 0; |
| 116 | mupd->FspmConfig.ChannelsSlicesEnable = 0; |
| 117 | mupd->FspmConfig.MinRefRate2xEnable = 0; |
| 118 | mupd->FspmConfig.DualRankSupportEnable = 1; |
| 119 | mupd->FspmConfig.DisableFastBoot = 0; |
| 120 | mupd->FspmConfig.RmtMode = 0; |
| 121 | mupd->FspmConfig.MemorySizeLimit = 0; |
| 122 | mupd->FspmConfig.LowMemoryMaxValue = 0; |
| 123 | mupd->FspmConfig.HighMemoryMaxValue = 0; |
| 124 | |
| 125 | if (IS_ENABLED(CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1)) |
| 126 | rvp1_fill_memory_params(mupd); |
| 127 | else |
| 128 | rvp2_fill_memory_params(mupd); |
| 129 | } |