Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2015 Google Inc. |
| 5 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 17 | #include <device/mmio.h> |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 18 | #include <arch/mmu.h> |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 19 | #include <bootmode.h> |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 20 | #include <boot/coreboot_tables.h> |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 21 | #include <delay.h> |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 22 | #include <device/device.h> |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 23 | #include <device/i2c_simple.h> |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 24 | #include <soc/addressmap.h> |
| 25 | #include <soc/clk_rst.h> |
| 26 | #include <soc/clock.h> |
| 27 | #include <soc/funitcfg.h> |
| 28 | #include <soc/padconfig.h> |
| 29 | #include <soc/nvidia/tegra/i2c.h> |
| 30 | #include <soc/nvidia/tegra/pingroup.h> |
| 31 | #include <soc/nvidia/tegra/dc.h> |
| 32 | #include <soc/display.h> |
| 33 | #include <soc/mtc.h> |
| 34 | #include <soc/pmc.h> |
| 35 | #include <soc/power.h> |
| 36 | |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 37 | #include "gpio.h" |
| 38 | #include "pmic.h" |
| 39 | |
| 40 | static const struct pad_config padcfgs[] = { |
| 41 | PAD_CFG_GPIO_INPUT(USB_VBUS_EN1, PINMUX_PULL_NONE | PINMUX_PARKED | |
| 42 | PINMUX_INPUT_ENABLE | PINMUX_LPDR | PINMUX_IO_HV), |
| 43 | }; |
| 44 | |
| 45 | static const struct pad_config audio_codec_pads[] = { |
| 46 | /* GPIO_X1_AUD(BB3) is CODEC_RST_L and DMIC1_DAT(E1) is AUDIO_ENABLE */ |
| 47 | PAD_CFG_GPIO_OUT1(GPIO_X1_AUD, PINMUX_PULL_DOWN), |
| 48 | PAD_CFG_GPIO_OUT1(DMIC1_DAT, PINMUX_PULL_DOWN), |
| 49 | }; |
| 50 | |
| 51 | static const struct pad_config i2s1_pad[] = { |
| 52 | /* I2S1 */ |
| 53 | PAD_CFG_SFIO(DAP1_SCLK, PINMUX_INPUT_ENABLE, I2S1), |
| 54 | PAD_CFG_SFIO(DAP1_FS, PINMUX_INPUT_ENABLE, I2S1), |
| 55 | PAD_CFG_SFIO(DAP1_DOUT, PINMUX_INPUT_ENABLE, I2S1), |
| 56 | PAD_CFG_SFIO(DAP1_DIN, PINMUX_INPUT_ENABLE | PINMUX_TRISTATE, I2S1), |
| 57 | /* codec MCLK via AUD SFIO */ |
| 58 | PAD_CFG_SFIO(AUD_MCLK, PINMUX_PULL_NONE, AUD), |
| 59 | }; |
| 60 | |
| 61 | static const struct funit_cfg audio_funit[] = { |
| 62 | /* We need 1.5MHz for I2S1. So we use CLK_M */ |
| 63 | FUNIT_CFG(I2S1, CLK_M, 1500, i2s1_pad, ARRAY_SIZE(i2s1_pad)), |
| 64 | }; |
| 65 | |
| 66 | static const struct funit_cfg funits[] = { |
| 67 | FUNIT_CFG_USB(USBD), |
| 68 | FUNIT_CFG(SDMMC4, PLLP, 48000, NULL, 0), |
| 69 | /* I2C6 for audio, temp sensor, etc. Enable codec via GPIOs/muxes */ |
| 70 | FUNIT_CFG(I2C6, PLLP, 400, audio_codec_pads, ARRAY_SIZE(audio_codec_pads)), |
| 71 | }; |
| 72 | |
| 73 | /* Audio init: clocks and enables/resets */ |
| 74 | static void setup_audio(void) |
| 75 | { |
| 76 | /* Audio codec (RT5677) uses 12MHz CLK1/EXTPERIPH1 */ |
| 77 | clock_configure_source(extperiph1, PLLP, 12000); |
| 78 | |
| 79 | /* Configure AUD_MCLK pad drive strength */ |
| 80 | write32((unsigned int *)TEGRA_APB_MISC_GP_BASE + 0xF4, |
| 81 | (0x10 << PINGROUP_DRVUP_SHIFT | 0x10 << PINGROUP_DRVDN_SHIFT)); |
| 82 | |
| 83 | /* Set up audio peripheral clocks/muxes */ |
| 84 | soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit)); |
| 85 | |
| 86 | /* Enable CLK1_OUT */ |
| 87 | clock_external_output(1); |
| 88 | |
| 89 | /* |
| 90 | * As per NVIDIA hardware team, we need to take ALL audio devices |
| 91 | * connected to AHUB (AUDIO, APB2APE, I2S, SPDIF, etc.) out of reset |
| 92 | * and clock-enabled, otherwise reading AHUB devices (in our case, |
| 93 | * I2S/APBIF/AUDIO<XBAR>) will hang. |
| 94 | */ |
| 95 | soc_configure_ape(); |
| 96 | clock_enable_audio(); |
| 97 | } |
| 98 | |
| 99 | static const struct pad_config lcd_gpio_padcfgs[] = { |
| 100 | /* LCD_EN */ |
| 101 | PAD_CFG_GPIO_OUT0(LCD_BL_EN, PINMUX_PULL_UP), |
| 102 | /* LCD_RST_L */ |
| 103 | PAD_CFG_GPIO_OUT0(LCD_RST, PINMUX_PULL_UP), |
| 104 | /* EN_VDD_LCD */ |
| 105 | PAD_CFG_GPIO_OUT0(LCD_GPIO2, PINMUX_PULL_NONE), |
| 106 | /* EN_VDD18_LCD */ |
| 107 | PAD_CFG_GPIO_OUT0(LCD_GPIO1, PINMUX_PULL_NONE), |
| 108 | }; |
| 109 | |
| 110 | static void configure_display_clocks(void) |
| 111 | { |
| 112 | u32 lclks = CLK_L_HOST1X | CLK_L_DISP1; /* dc */ |
| 113 | u32 hclks = CLK_H_MIPI_CAL | CLK_H_DSI; /* mipi phy, mipi-dsi a */ |
| 114 | u32 uclks = CLK_U_DSIB; /* mipi-dsi b */ |
| 115 | u32 xclks = CLK_X_UART_FST_MIPI_CAL; /* uart_fst_mipi_cal */ |
| 116 | |
| 117 | clock_enable_clear_reset(lclks, hclks, uclks, 0, 0, xclks, 0); |
| 118 | |
| 119 | /* Give clocks time to stabilize. */ |
| 120 | udelay(IO_STABILIZATION_DELAY); |
| 121 | |
| 122 | /* CLK72MHZ_CLK_SRC */ |
| 123 | clock_configure_source(uart_fst_mipi_cal, PLLP_OUT3, 68000); |
| 124 | } |
| 125 | |
| 126 | static int enable_lcd_vdd(void) |
| 127 | { |
| 128 | /* Set 1.20V to power AVDD_DSI_CSI */ |
| 129 | /* LD0: 1.20v CNF1: 0x0d */ |
| 130 | pmic_write_reg_77620(I2CPWR_BUS, MAX77620_CNFG1_L0_REG, 0xd0, 1); |
| 131 | |
| 132 | /* Enable VDD_LCD */ |
| 133 | gpio_set(EN_VDD_LCD, 1); |
| 134 | /* wait for 2ms */ |
| 135 | mdelay(2); |
| 136 | |
| 137 | /* Enable PP1800_LCDIO to panel */ |
| 138 | gpio_set(EN_VDD18_LCD, 1); |
| 139 | /* wait for 1ms */ |
| 140 | mdelay(1); |
| 141 | |
| 142 | /* Set panel EN and RST signals */ |
| 143 | gpio_set(LCD_EN, 1); /* enable */ |
| 144 | /* wait for min 10ms */ |
| 145 | mdelay(10); |
| 146 | gpio_set(LCD_RST_L, 1); /* clear reset */ |
| 147 | /* wait for min 3ms */ |
| 148 | mdelay(3); |
| 149 | |
| 150 | return 0; |
| 151 | } |
| 152 | |
| 153 | static int configure_display_blocks(void) |
| 154 | { |
| 155 | /* enable display related clocks */ |
| 156 | configure_display_clocks(); |
| 157 | |
| 158 | /* configure panel gpio pads */ |
| 159 | soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs)); |
| 160 | |
| 161 | /* set and enable panel related vdd */ |
| 162 | if (enable_lcd_vdd()) |
| 163 | return -1; |
| 164 | |
| 165 | return 0; |
| 166 | } |
| 167 | |
| 168 | static void powergate_unused_partitions(void) |
| 169 | { |
| 170 | static const uint32_t partitions[] = { |
| 171 | POWER_PARTID_PCX, |
| 172 | POWER_PARTID_SAX, |
Andrew Bresticker | 3bc4373 | 2015-07-20 10:34:06 -0700 | [diff] [blame] | 173 | POWER_PARTID_XUSBA, |
| 174 | POWER_PARTID_XUSBB, |
| 175 | POWER_PARTID_XUSBC, |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 176 | POWER_PARTID_NVDEC, |
| 177 | POWER_PARTID_NVJPG, |
| 178 | POWER_PARTID_DFD, |
| 179 | }; |
| 180 | |
| 181 | int i; |
| 182 | for (i = 0; i < ARRAY_SIZE(partitions); i++) |
| 183 | power_gate_partition(partitions[i]); |
| 184 | } |
| 185 | |
Elyes HAOUAS | d129d43 | 2018-05-04 20:23:33 +0200 | [diff] [blame] | 186 | static void mainboard_init(struct device *dev) |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 187 | { |
| 188 | soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); |
| 189 | soc_configure_funits(funits, ARRAY_SIZE(funits)); |
| 190 | |
| 191 | /* I2C6 bus (audio, etc.) */ |
| 192 | soc_configure_i2c6pad(); |
| 193 | i2c_init(I2C6_BUS); |
| 194 | setup_audio(); |
| 195 | |
| 196 | /* if panel needs to bringup */ |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 197 | if (display_init_required()) |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 198 | configure_display_blocks(); |
| 199 | |
| 200 | powergate_unused_partitions(); |
| 201 | } |
| 202 | |
Elyes HAOUAS | d129d43 | 2018-05-04 20:23:33 +0200 | [diff] [blame] | 203 | void display_startup(struct device *dev) |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 204 | { |
| 205 | dsi_display_startup(dev); |
| 206 | } |
| 207 | |
Elyes HAOUAS | d129d43 | 2018-05-04 20:23:33 +0200 | [diff] [blame] | 208 | static void mainboard_enable(struct device *dev) |
Patrick Georgi | 4d6ad83 | 2015-06-22 19:43:18 +0200 | [diff] [blame] | 209 | { |
| 210 | dev->ops->init = &mainboard_init; |
| 211 | } |
| 212 | |
| 213 | struct chip_operations mainboard_ops = { |
| 214 | .name = "smaug", |
| 215 | .enable_dev = mainboard_enable, |
| 216 | }; |
| 217 | |
| 218 | void lb_board(struct lb_header *header) |
| 219 | { |
| 220 | #if IS_ENABLED(CONFIG_CHROMEOS) |
| 221 | lb_table_add_serialno_from_vpd(header); |
| 222 | #endif |
| 223 | soc_add_mtc(header); |
| 224 | } |