Yidi Lin | 65873ca | 2015-07-31 17:10:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2015 MediaTek Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Yidi Lin | 65873ca | 2015-07-31 17:10:57 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef __MAINBOARD_GOOGLE_OAK_GPIO_H__ |
| 17 | #define __MAINBOARD_GOOGLE_OAK_GPIO_H__ |
Tristan Shieh | 71d227b | 2018-07-09 18:59:32 +0800 | [diff] [blame] | 18 | #include <soc/gpio.h> |
Yidi Lin | 65873ca | 2015-07-31 17:10:57 +0800 | [diff] [blame] | 19 | |
Tristan Shieh | 71d227b | 2018-07-09 18:59:32 +0800 | [diff] [blame] | 20 | #if IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN) |
| 21 | #define LID GPIO(KPROW1) |
| 22 | #define RAM_ID_1 GPIO(DSI_TE) |
| 23 | #define RAM_ID_2 GPIO(RDP1_A) |
| 24 | #else |
| 25 | #define LID ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? \ |
| 26 | GPIO(EINT12) : GPIO(SPI_CK)) |
| 27 | #define RAM_ID_1 GPIO(RCN_A) |
| 28 | #define RAM_ID_2 GPIO(RCP_A) |
| 29 | #endif |
Yidi Lin | 19318dd | 2016-03-16 16:59:17 +0800 | [diff] [blame] | 30 | |
Tristan Shieh | 71d227b | 2018-07-09 18:59:32 +0800 | [diff] [blame] | 31 | /* Board ID related GPIOS. */ |
| 32 | #define BOARD_ID_0 GPIO(RDN3_A) |
| 33 | #define BOARD_ID_1 GPIO(RDP3_A) |
| 34 | #define BOARD_ID_2 GPIO(RDN2_A) |
| 35 | /* RAM ID related GPIOS. */ |
| 36 | #define RAM_ID_0 GPIO(RDP2_A) |
| 37 | #define RAM_ID_3 GPIO(RDN1_A) |
| 38 | /* Write Protect */ |
| 39 | #define WRITE_PROTECT GPIO(EINT4) |
| 40 | /* Power button */ |
| 41 | #define POWER_BUTTON GPIO(EINT14) |
| 42 | /* EC Interrupt */ |
| 43 | #define EC_IRQ GPIO(EINT0) |
| 44 | /* EC in RW signal */ |
| 45 | #define EC_IN_RW GPIO(DAIPCMIN) |
| 46 | /* EC AP suspend */ |
| 47 | #define EC_SUSPEND_L GPIO(KPROW1) |
| 48 | /* Cr50 interrupt */ |
| 49 | #define CR50_IRQ GPIO(EINT16) |
Yidi Lin | 65873ca | 2015-07-31 17:10:57 +0800 | [diff] [blame] | 50 | |
| 51 | void setup_chromeos_gpios(void); |
| 52 | |
| 53 | #endif /* __MAINBOARD_GOOGLE_OAK_GPIO_H__ */ |