Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/cache.h> |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 17 | #include <arch/exception.h> |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 18 | #include <cbmem.h> |
| 19 | #include <console/console.h> |
Daisuke Nojiri | 512bfbc | 2014-08-15 17:07:39 -0700 | [diff] [blame] | 20 | #include <reset.h> |
Aaron Durbin | e4f3e7a | 2015-03-17 13:25:19 -0500 | [diff] [blame] | 21 | #include <program_loading.h> |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 22 | #include <soc/addressmap.h> |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 23 | #include <soc/cache.h> |
| 24 | #include <soc/clk_rst.h> |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 25 | #include <soc/clock.h> |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 26 | #include <soc/display.h> |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 27 | #include <soc/early_configs.h> |
| 28 | #include <soc/nvidia/tegra/i2c.h> |
| 29 | #include <soc/nvidia/tegra124/chip.h> |
| 30 | #include <soc/power.h> |
| 31 | #include <soc/sdram.h> |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 32 | #include <symbols.h> |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 33 | #include <timestamp.h> |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 34 | #include <vendorcode/google/chromeos/chromeos.h> |
| 35 | |
| 36 | #include "sdram_configs.h" |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 37 | |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 38 | static void __attribute__((noinline)) romstage(void) |
| 39 | { |
Kyösti Mälkki | f48b38b | 2014-12-31 08:50:36 +0200 | [diff] [blame] | 40 | timestamp_init(0); |
| 41 | timestamp_add_now(TS_START_ROMSTAGE); |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 42 | |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 43 | console_init(); |
| 44 | exception_init(); |
| 45 | |
| 46 | sdram_init(get_sdram_config()); |
| 47 | |
| 48 | /* used for MMU and CBMEM setup, in MB */ |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 49 | u32 dram_start_mb = (uintptr_t)_dram/MiB; |
| 50 | u32 dram_end_mb = sdram_max_addressable_mb(); |
| 51 | u32 dram_size_mb = dram_end_mb - dram_start_mb; |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 52 | |
Martin Roth | 356b519 | 2017-06-24 21:53:37 -0600 | [diff] [blame] | 53 | #if !IS_ENABLED(CONFIG_VBOOT) |
Daisuke Nojiri | efddcfb | 2014-09-04 09:55:34 -0700 | [diff] [blame] | 54 | configure_l2_cache(); |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 55 | mmu_init(); |
| 56 | /* Device memory below DRAM is uncached. */ |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 57 | mmu_config_range(0, dram_start_mb, DCACHE_OFF); |
| 58 | /* SRAM is cached. MMU code will round size up to page size. */ |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 59 | mmu_config_range((uintptr_t)_sram/MiB, |
| 60 | DIV_ROUND_UP(REGION_SIZE(sram), MiB), |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 61 | DCACHE_WRITEBACK); |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 62 | /* The space above DRAM is uncached. */ |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 63 | if (dram_end_mb < 4096) |
| 64 | mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 65 | mmu_disable_range(0, 1); |
| 66 | dcache_mmu_enable(); |
Daisuke Nojiri | efddcfb | 2014-09-04 09:55:34 -0700 | [diff] [blame] | 67 | #endif |
| 68 | |
| 69 | /* DRAM is cached. */ |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 70 | mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); |
Daisuke Nojiri | efddcfb | 2014-09-04 09:55:34 -0700 | [diff] [blame] | 71 | /* A window for DMA is uncached. */ |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 72 | mmu_config_range((uintptr_t)_dma_coherent/MiB, |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 73 | REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 74 | |
Gabe Black | c852206 | 2014-05-06 15:44:14 -0700 | [diff] [blame] | 75 | /* |
| 76 | * A watchdog reset only resets part of the system so it ends up in |
| 77 | * a funny state. If that happens, we need to reset the whole machine. |
| 78 | */ |
| 79 | if (power_reset_status() == POWER_RESET_WATCHDOG) { |
| 80 | printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); |
Nico Huber | e879136 | 2018-10-06 17:53:14 +0200 | [diff] [blame] | 81 | board_reset(); |
Gabe Black | c852206 | 2014-05-06 15:44:14 -0700 | [diff] [blame] | 82 | } |
| 83 | |
Patrick Georgi | 3756de0 | 2015-06-30 14:32:15 +0200 | [diff] [blame] | 84 | /* FIXME: this may require coordination with moving timestamps */ |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 85 | cbmem_initialize_empty(); |
| 86 | |
Paul Kocialkowski | 7b0e0d9 | 2016-06-27 18:17:14 +0200 | [diff] [blame] | 87 | /* This was already called from verstage in vboot context. */ |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 88 | if (!IS_ENABLED(CONFIG_VBOOT)) |
Paul Kocialkowski | 7b0e0d9 | 2016-06-27 18:17:14 +0200 | [diff] [blame] | 89 | early_mainboard_init(); |
Gabe Black | 4a12cfe | 2014-03-24 21:24:24 -0700 | [diff] [blame] | 90 | |
Aaron Durbin | e4f3e7a | 2015-03-17 13:25:19 -0500 | [diff] [blame] | 91 | run_ramstage(); |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | /* Stub to force arm_init_caches to the top, before any stack/memory accesses */ |
| 95 | void main(void) |
| 96 | { |
Martin Roth | 356b519 | 2017-06-24 21:53:37 -0600 | [diff] [blame] | 97 | #if !IS_ENABLED(CONFIG_VBOOT) |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 98 | asm volatile ("bl arm_init_caches" |
| 99 | ::: "r0","r1","r2","r3","r4","r5","ip"); |
Daisuke Nojiri | efddcfb | 2014-09-04 09:55:34 -0700 | [diff] [blame] | 100 | #endif |
Tom Warren | 4e16a2e | 2014-03-19 14:19:09 -0700 | [diff] [blame] | 101 | romstage(); |
| 102 | } |