blob: 83757a850d1f42b25893141cd4973cf6e86ece37 [file] [log] [blame]
Marshall Dawson79df1fb2017-10-04 12:34:17 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2016 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <arch/acpi.h>
18#include <cpu/x86/smm.h>
19#include <ec/google/chromeec/smm.h>
Marc Jonesee03dc22018-07-14 17:32:04 -060020#include <gpio.h>
Marshall Dawson79df1fb2017-10-04 12:34:17 -060021#include <soc/smi.h>
Martin Roth6c623ca2017-11-16 22:14:53 -070022#include <variant/ec.h>
Marc Jonesee03dc22018-07-14 17:32:04 -060023#include <variant/gpio.h>
Marshall Dawson79df1fb2017-10-04 12:34:17 -060024
Raul E Rangel8173ad12018-05-25 16:11:39 -060025void mainboard_smi_gpi(u32 gpi_sts)
26{
27 if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
28 if (gpi_sts & (1 << EC_SMI_GPI))
29 chromeec_smi_process_events();
30}
31
Marshall Dawsonf8bf9a72017-10-04 15:13:52 -060032void mainboard_smi_sleep(u8 slp_typ)
33{
34 if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
35 chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
36 MAINBOARD_EC_S5_WAKE_EVENTS);
37}
38
Marshall Dawson79df1fb2017-10-04 12:34:17 -060039int mainboard_smi_apmc(u8 apmc)
40{
41 if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
42 chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
43 MAINBOARD_EC_SMI_EVENTS);
Marc Jonesee03dc22018-07-14 17:32:04 -060044
45 /* Enable backlight - GPIO active low */
46 gpio_set(GPIO_133, 0);
47
Marshall Dawson79df1fb2017-10-04 12:34:17 -060048 return 0;
49}