Lee Leahy | 89b5fbd | 2015-05-11 17:24:31 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 89b5fbd | 2015-05-11 17:24:31 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Lee Leahy | 89b5fbd | 2015-05-11 17:24:31 -0700 | [diff] [blame] | 17 | #include <soc/romstage.h> |
Matt DeVillier | f2fc497 | 2017-10-03 15:39:22 -0500 | [diff] [blame] | 18 | #include <baseboard/variants.h> |
Matt DeVillier | 4f20a4a | 2017-08-20 17:56:48 -0500 | [diff] [blame] | 19 | #include <chip.h> |
Lee Leahy | 89b5fbd | 2015-05-11 17:24:31 -0700 | [diff] [blame] | 20 | |
| 21 | /* All FSP specific code goes in this block */ |
| 22 | void mainboard_romstage_entry(struct romstage_params *rp) |
| 23 | { |
| 24 | struct pei_data *ps = rp->pei_data; |
| 25 | |
| 26 | mainboard_fill_spd_data(ps); |
| 27 | |
| 28 | /* Call back into chipset code with platform values updated. */ |
| 29 | romstage_common(rp); |
| 30 | } |
| 31 | |
Lee Leahy | 89b5fbd | 2015-05-11 17:24:31 -0700 | [diff] [blame] | 32 | void mainboard_memory_init_params(struct romstage_params *params, |
| 33 | MEMORY_INIT_UPD *memory_params) |
| 34 | { |
| 35 | /* Update SPD data */ |
Matt DeVillier | b3937bb | 2017-12-07 20:34:08 -0600 | [diff] [blame] | 36 | if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { |
Matt DeVillier | f2fc497 | 2017-10-03 15:39:22 -0500 | [diff] [blame] | 37 | memory_params->PcdMemoryTypeEnable = MEM_DDR3; |
Matt DeVillier | b3937bb | 2017-12-07 20:34:08 -0600 | [diff] [blame] | 38 | memory_params->PcdMemorySpdPtr = |
| 39 | (u32)params->pei_data->spd_data_ch0; |
| 40 | } else |
Matt DeVillier | 4f20a4a | 2017-08-20 17:56:48 -0500 | [diff] [blame] | 41 | memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; |
Matt DeVillier | b3937bb | 2017-12-07 20:34:08 -0600 | [diff] [blame] | 42 | |
Lee Leahy | 89b5fbd | 2015-05-11 17:24:31 -0700 | [diff] [blame] | 43 | memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; |
| 44 | memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; |
Matt DeVillier | f2fc497 | 2017-10-03 15:39:22 -0500 | [diff] [blame] | 45 | |
| 46 | /* Variant-specific memory params */ |
| 47 | variant_memory_init_params(memory_params); |
| 48 | } |
| 49 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 50 | __weak |
Matt DeVillier | f2fc497 | 2017-10-03 15:39:22 -0500 | [diff] [blame] | 51 | void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) |
| 52 | { |
Lee Leahy | 89b5fbd | 2015-05-11 17:24:31 -0700 | [diff] [blame] | 53 | } |