blob: f7b51a94230f86f990acbdeacea1e8d79cf33a31 [file] [log] [blame]
Matt DeVillier81ae67a2016-11-08 15:04:30 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Matt DeVillier81ae67a2016-11-08 15:04:30 -060016#include <string.h>
17#include <types.h>
18#include <arch/acpi.h>
19#include <arch/acpigen.h>
20#include <arch/ioapic.h>
21#include <arch/smp/mpspec.h>
Matt DeVillier81ae67a2016-11-08 15:04:30 -060022#include <device/device.h>
23#include <device/pci.h>
Matt DeVillier81ae67a2016-11-08 15:04:30 -060024#include <ec/google/chromeec/ec.h>
25#include <southbridge/intel/lynxpoint/nvs.h>
26#include <southbridge/intel/lynxpoint/pch.h>
27#include <vendorcode/google/chromeos/gnvs.h>
28#include <variant/thermal.h>
29
30static void acpi_update_thermal_table(global_nvs_t *gnvs)
31{
32 gnvs->f4of = FAN4_THRESHOLD_OFF;
33 gnvs->f4on = FAN4_THRESHOLD_ON;
34 gnvs->f4pw = FAN4_PWM;
35
36 gnvs->f3of = FAN3_THRESHOLD_OFF;
37 gnvs->f3on = FAN3_THRESHOLD_ON;
38 gnvs->f3pw = FAN3_PWM;
39
40 gnvs->f2of = FAN2_THRESHOLD_OFF;
41 gnvs->f2on = FAN2_THRESHOLD_ON;
42 gnvs->f2pw = FAN2_PWM;
43
44 gnvs->f1of = FAN1_THRESHOLD_OFF;
45 gnvs->f1on = FAN1_THRESHOLD_ON;
46 gnvs->f1pw = FAN1_PWM;
47
48 gnvs->f0of = FAN0_THRESHOLD_OFF;
49 gnvs->f0on = FAN0_THRESHOLD_ON;
50 gnvs->f0pw = FAN0_PWM;
51
52 gnvs->tcrt = CRITICAL_TEMPERATURE;
53 gnvs->tpsv = PASSIVE_TEMPERATURE;
54 gnvs->tmax = MAX_TEMPERATURE;
55 gnvs->flvl = 5;
56}
57
58void acpi_create_gnvs(global_nvs_t *gnvs)
59{
60 /* Enable USB ports in S3 */
61 gnvs->s3u0 = 1;
62 gnvs->s3u1 = 1;
63
64 /* Disable USB ports in S5 */
65 gnvs->s5u0 = 0;
66 gnvs->s5u1 = 0;
67
68 /* TPM Present */
69 gnvs->tpmp = 1;
70
71
Martin Roth356b5192017-06-24 21:53:37 -060072#if IS_ENABLED(CONFIG_CHROMEOS)
Matt DeVillier81ae67a2016-11-08 15:04:30 -060073 // SuperIO is always RO
74 gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
75#endif
76
77 acpi_update_thermal_table(gnvs);
78}