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Timothy Pearson4551b682015-11-24 14:12:08 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 * Copyright (C) 2015 Raptor Engineering
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
Timothy Pearson4551b682015-11-24 14:12:08 -060017#include <arch/smp/mpspec.h>
18#include <device/pci.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020019#include <device/pci_ops.h>
Timothy Pearson4551b682015-11-24 14:12:08 -060020#include <string.h>
21#include <stdint.h>
22#include <cpu/amd/amdfam10_sysconf.h>
23
Timothy Pearson4551b682015-11-24 14:12:08 -060024static void *smp_write_config_table(void *v)
25{
26 struct mp_config_table *mc;
27 int bus_isa;
Kyösti Mälkki22521ab2019-01-04 05:16:38 +020028 u32 apicid_sp5100;
Timothy Pearson4551b682015-11-24 14:12:08 -060029 u32 apicid_sr5650;
Elyes HAOUAS02b05d12018-05-04 20:00:08 +020030 struct device *dev;
Timothy Pearson4551b682015-11-24 14:12:08 -060031 uint8_t sp5100_bus_number;
32
33 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
34
35 mptable_init(mc, LOCAL_APIC_ADDR);
36
37 smp_write_processors(mc);
38
Timothy Pearson4551b682015-11-24 14:12:08 -060039 if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
40 apicid_sp5100 = 0x0;
41 else
42 apicid_sp5100 = 0x20;
43 apicid_sr5650 = apicid_sp5100 + 1;
44
45 mptable_write_buses(mc, NULL, &bus_isa);
46 /* I/O APICs: APIC ID Version State Address */
47 {
48 uint32_t *dword_ptr;
49 uint32_t dword;
50 uint16_t word;
51 uint8_t byte;
52
53 sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
54
Kyösti Mälkki228746b2019-01-03 11:38:51 +020055 dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(0x14, 0));
Timothy Pearson4551b682015-11-24 14:12:08 -060056 if (dev) {
57 dword_ptr = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
58 smp_write_ioapic(mc, apicid_sp5100, 0x11, dword_ptr);
59
60 /* Initialize interrupt mapping */
61 /* USB 1 & 2 */
62 word = pci_read_config16(dev, 0xbe);
63 word &= ~0x3f3f;
64 word |= 0x0; /* 0: INTA, ...., 7: INTH */
65 word |= (0x1 << 3); /* 0: INTA, ...., 7: INTH */
66 word |= (0x2 << 8); /* 0: INTA, ...., 7: INTH */
67 word |= (0x3 << 11); /* 0: INTA, ...., 7: INTH */
68 pci_write_config16(dev, 0xbe, word);
69
70 /* USB 3 */
71 byte = pci_read_config8(dev, 0x63);
72 byte &= 0xf8;
73 byte |= (0x2 << 4); /* 0: INTA, ...., 7: INTH */
74 pci_write_config8(dev, 0x63, byte);
75
76 dword = pci_read_config32(dev, 0xac);
77
78 /* SATA */
79 dword &= ~(7 << 26);
80 dword |= (0x6 << 26); /* 0: INTA, ...., 7: INTH */
81
82 /* Hide IDE */
83 dword &= ~(0x00080000);
84
Elyes HAOUAS6350a2e2016-09-16 20:49:38 +020085 /* dword_ptr |= 1 << 22; PIC and APIC co exists */
Timothy Pearson4551b682015-11-24 14:12:08 -060086 pci_write_config32(dev, 0xac, dword);
87
88 /*
89 * 00:12.0: PROG SATA : INT F
90 * 00:13.0: INTA USB_0
91 * 00:13.1: INTB USB_1
92 * 00:13.2: INTC USB_2
93 * 00:13.3: INTD USB_3
94 * 00:13.4: INTC USB_4
95 * 00:13.5: INTD USB2
96 * 00:14.1: INTA IDE
97 * 00:14.2: Prog HDA : INT E
98 * 00:14.5: INTB ACI
99 * 00:14.6: INTB MCI
100 */
101 }
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300102 dev = pcidev_on_root(0, 0);
Timothy Pearson4551b682015-11-24 14:12:08 -0600103 if (dev) {
104 pci_write_config32(dev, 0xF8, 0x1);
105 dword_ptr = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
106 smp_write_ioapic(mc, apicid_sr5650, 0x11, dword_ptr);
107 }
108 }
109
110 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
111#define IO_LOCAL_INT(type, intr, apicid, pin) \
112 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
113
114 mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
115
116 /* SR5650 devices */
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((0)<<2)|(2)), apicid_sr5650, 31); /* Device 0 Function 2 (LNKA, APIC pin 31) */
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE, APIC pin 28) */
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF, APIC pin 28) */
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG, APIC pin 29) */
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */
Timothy Pearson4551b682015-11-24 14:12:08 -0600124
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300125 dev = pcidev_on_root(0x2, 0);
Timothy Pearson4551b682015-11-24 14:12:08 -0600126 if (dev && dev->enabled) {
127 uint8_t bus_pci = dev->link_list->secondary;
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x2)|(0)), apicid_sr5650, 0); /* card behind dev2 */
129 }
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300130 dev = pcidev_on_root(0x4, 0);
Timothy Pearson4551b682015-11-24 14:12:08 -0600131 if (dev && dev->enabled) {
132 uint8_t bus_pci = dev->link_list->secondary;
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x4)|(0)), apicid_sr5650, 0); /* PIKE */
134 }
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300135 dev = pcidev_on_root(0x9, 0);
Timothy Pearson4551b682015-11-24 14:12:08 -0600136 if (dev && dev->enabled) {
137 uint8_t bus_pci = dev->link_list->secondary;
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0x9)|(0)), apicid_sr5650, 23); /* NIC A */
139 }
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300140 dev = pcidev_on_root(0xa, 0);
Timothy Pearson4551b682015-11-24 14:12:08 -0600141 if (dev && dev->enabled) {
142 uint8_t bus_pci = dev->link_list->secondary;
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xa)|(0)), apicid_sr5650, 24); /* NIC B */
144 }
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300145 dev = pcidev_on_root(0xb, 0);
Timothy Pearson4551b682015-11-24 14:12:08 -0600146 if (dev && dev->enabled) {
147 uint8_t bus_pci = dev->link_list->secondary;
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xb)|(0)), apicid_sr5650, 0); /* card behind dev11 */
149 }
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300150 dev = pcidev_on_root(0xc, 0);
Timothy Pearson4551b682015-11-24 14:12:08 -0600151 if (dev && dev->enabled) {
152 uint8_t bus_pci = dev->link_list->secondary;
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */
154 }
Timothy Pearson4551b682015-11-24 14:12:08 -0600155
156 /* PCI interrupts are level triggered, and are
157 * associated with a specific bus/device/function tuple.
158 */
159#define PCI_INT(bus, dev, interrupt_signal, pin) \
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(interrupt_signal)), apicid_sp5100, (pin))
161
162 /* USB1 */
163 PCI_INT(sp5100_bus_number, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
164 PCI_INT(sp5100_bus_number, 0x12, 0x1, 0x11); /* OHCI1 Port 3~5 */
165
166 /* USB2 */
167 PCI_INT(sp5100_bus_number, 0x13, 0x0, 0x12); /* OHCI0 Port 6~8 */
168 PCI_INT(sp5100_bus_number, 0x13, 0x1, 0x13); /* EHCI Port 6~11 */
169
170 /* USB3 */
171 PCI_INT(sp5100_bus_number, 0x14, 0x3, 0x12); /* OHCI0 Port 12~13 */
172
173 /* SATA */
174 PCI_INT(sp5100_bus_number, 0x11, 0x0, 0x16); /* 6, INTG */
175
176 /* PCI slots */
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300177 dev = pcidev_on_root(0x14, 4);
Timothy Pearson4551b682015-11-24 14:12:08 -0600178 if (dev && dev->enabled) {
179 u8 bus_pci = dev->link_list->secondary;
180
Timothy Pearsonb251a502015-11-24 14:17:49 -0600181 /* PCI_SLOT 0 */
182 PCI_INT(bus_pci, 0x1, 0x0, 0x14);
183 PCI_INT(bus_pci, 0x1, 0x1, 0x15);
184 PCI_INT(bus_pci, 0x1, 0x2, 0x16);
185 PCI_INT(bus_pci, 0x1, 0x3, 0x17);
Timothy Pearson4551b682015-11-24 14:12:08 -0600186
Timothy Pearsonb251a502015-11-24 14:17:49 -0600187 /* PCI_SLOT 1 */
188 PCI_INT(bus_pci, 0x2, 0x0, 0x15);
189 PCI_INT(bus_pci, 0x2, 0x1, 0x16);
190 PCI_INT(bus_pci, 0x2, 0x2, 0x17);
191 PCI_INT(bus_pci, 0x2, 0x3, 0x14);
Timothy Pearson4551b682015-11-24 14:12:08 -0600192
Timothy Pearsonb251a502015-11-24 14:17:49 -0600193 /* PCI_SLOT 2 */
Timothy Pearson4551b682015-11-24 14:12:08 -0600194 PCI_INT(bus_pci, 0x3, 0x0, 0x16);
195 PCI_INT(bus_pci, 0x3, 0x1, 0x17);
196 PCI_INT(bus_pci, 0x3, 0x2, 0x14);
197 PCI_INT(bus_pci, 0x3, 0x3, 0x15);
Timothy Pearsonb251a502015-11-24 14:17:49 -0600198
199 /* VGA */
200 PCI_INT(bus_pci, 0x5, 0x0, 0x17);
201 PCI_INT(bus_pci, 0x5, 0x1, 0x14);
202 PCI_INT(bus_pci, 0x5, 0x2, 0x15);
203 PCI_INT(bus_pci, 0x5, 0x3, 0x16);
Timothy Pearson4551b682015-11-24 14:12:08 -0600204 }
205
206 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
207 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
208 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
209 /* There is no extension information... */
210
211 /* Compute the checksums */
212 return mptable_finalize(mc);
213}
214
215unsigned long write_smp_table(unsigned long addr)
216{
217 void *v;
218 v = smp_write_floating_table(addr, 0);
219 return (unsigned long)smp_write_config_table(v);
220}