Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 17 | #include <AGESA.h> |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 18 | #include <PlatformMemoryConfiguration.h> |
| 19 | |
| 20 | #include <northbridge/amd/agesa/state_machine.h> |
| 21 | |
| 22 | static const PCIe_PORT_DESCRIPTOR PortList[] = { |
| 23 | { |
| 24 | 0, |
| 25 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), |
| 26 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, |
| 27 | HotplugDisabled, |
| 28 | PcieGenMaxSupported, |
| 29 | PcieGenMaxSupported, |
| 30 | AspmDisabled, 0x01, 0) |
| 31 | }, |
| 32 | /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ |
| 33 | { |
| 34 | 0, |
| 35 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), |
| 36 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, |
| 37 | HotplugDisabled, |
| 38 | PcieGenMaxSupported, |
| 39 | PcieGenMaxSupported, |
| 40 | AspmDisabled, 0x02, 0) |
| 41 | }, |
| 42 | /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ |
| 43 | { |
| 44 | 0, |
| 45 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), |
| 46 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, |
| 47 | HotplugDisabled, |
| 48 | PcieGenMaxSupported, |
| 49 | PcieGenMaxSupported, |
| 50 | AspmDisabled, 0x03, 0) |
| 51 | }, |
| 52 | /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ |
| 53 | { |
| 54 | 0, |
| 55 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), |
| 56 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, |
| 57 | HotplugDisabled, |
| 58 | PcieGenMaxSupported, |
| 59 | PcieGenMaxSupported, |
| 60 | AspmDisabled, 0x04, 0) |
| 61 | }, |
| 62 | /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ |
| 63 | { |
| 64 | DESCRIPTOR_TERMINATE_LIST, |
| 65 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), |
| 66 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, |
| 67 | HotplugDisabled, |
| 68 | PcieGenMaxSupported, |
| 69 | PcieGenMaxSupported, |
| 70 | AspmDisabled, 0x05, 0) |
| 71 | } |
| 72 | }; |
| 73 | |
| 74 | static const PCIe_DDI_DESCRIPTOR DdiList[] = { |
| 75 | /* DP0 to HDMI */ |
| 76 | { |
| 77 | 0, |
| 78 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), |
| 79 | PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) |
| 80 | }, |
| 81 | /* DP1 to DVI-D */ |
| 82 | { |
| 83 | 0, |
| 84 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), |
| 85 | PCIE_DDI_DATA_INITIALIZER(ConnectorTypeSingleLinkDVI, Aux2, Hdp2) |
| 86 | }, |
| 87 | /* DP2 to VGA */ |
| 88 | { |
| 89 | DESCRIPTOR_TERMINATE_LIST, |
| 90 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), |
| 91 | PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) |
| 92 | }, |
| 93 | }; |
| 94 | |
| 95 | static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { |
| 96 | .Flags = DESCRIPTOR_TERMINATE_LIST, |
| 97 | .SocketId = 0, |
| 98 | .PciePortList = PortList, |
| 99 | .DdiLinkList = DdiList |
| 100 | }; |
| 101 | |
| 102 | |
| 103 | void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) |
| 104 | { |
| 105 | FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; |
| 106 | |
| 107 | FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); |
| 108 | FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); |
| 109 | |
| 110 | FchReset->SataEnable = 1; |
| 111 | FchReset->IdeEnable = 0; |
| 112 | } |
| 113 | |
| 114 | void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) |
| 115 | { |
| 116 | InitEarly->GnbConfig.PcieComplexList = &PcieComplex; |
| 117 | } |
| 118 | |
| 119 | /*---------------------------------------------------------------------------------------- |
| 120 | * CUSTOMER OVERIDES MEMORY TABLE |
| 121 | *---------------------------------------------------------------------------------------- |
| 122 | */ |
| 123 | |
| 124 | /* |
| 125 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA |
| 126 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable |
| 127 | * is populated, AGESA will base its settings on the data from the table. Otherwise, it will |
| 128 | * use its default conservative settings. |
| 129 | */ |
| 130 | static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { |
| 131 | #define SEED_A 0x12 |
| 132 | HW_RXEN_SEED( |
| 133 | ANY_SOCKET, CHANNEL_A, ALL_DIMMS, |
| 134 | SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, |
| 135 | SEED_A), |
| 136 | |
| 137 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), |
| 138 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), |
| 139 | MOTHER_BOARD_LAYERS(LAYERS_4), |
| 140 | |
| 141 | MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), |
| 142 | CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ |
| 143 | ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), |
| 144 | CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), |
| 145 | |
| 146 | PSO_END |
| 147 | }; |
| 148 | |
| 149 | void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) |
| 150 | { |
| 151 | InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; |
| 152 | } |
| 153 | |
| 154 | void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) |
| 155 | { |
| 156 | /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ |
| 157 | InitMid->GnbMidConfiguration.iGpuVgaMode = 0; |
| 158 | } |