zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /** |
| 17 | * @file |
| 18 | * |
| 19 | * AMD User options selection for a Brazos platform solution system |
| 20 | * |
| 21 | * This file is placed in the user's platform directory and contains the |
| 22 | * build option selections desired for that platform. |
| 23 | * |
| 24 | * For Information about this file, see @ref platforminstall. |
| 25 | * |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 26 | */ |
| 27 | |
Edward O'Callaghan | d5339ae | 2014-07-07 19:58:53 +1000 | [diff] [blame] | 28 | #include <stdlib.h> |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 29 | #include <AGESA.h> |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 30 | |
Elyes HAOUAS | 8ab989e | 2016-07-30 17:46:17 +0200 | [diff] [blame] | 31 | /* Select the CPU family. */ |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 32 | #define INSTALL_FAMILY_10_SUPPORT FALSE |
| 33 | #define INSTALL_FAMILY_12_SUPPORT FALSE |
| 34 | #define INSTALL_FAMILY_14_SUPPORT FALSE |
| 35 | #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE |
| 36 | |
Elyes HAOUAS | 8ab989e | 2016-07-30 17:46:17 +0200 | [diff] [blame] | 37 | /* Select the CPU socket type. */ |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 38 | #define INSTALL_G34_SOCKET_SUPPORT FALSE |
| 39 | #define INSTALL_C32_SOCKET_SUPPORT FALSE |
| 40 | #define INSTALL_S1G3_SOCKET_SUPPORT FALSE |
| 41 | #define INSTALL_S1G4_SOCKET_SUPPORT FALSE |
| 42 | #define INSTALL_ASB2_SOCKET_SUPPORT FALSE |
| 43 | #define INSTALL_FS1_SOCKET_SUPPORT TRUE |
| 44 | #define INSTALL_FM1_SOCKET_SUPPORT FALSE |
| 45 | #define INSTALL_FP2_SOCKET_SUPPORT TRUE |
| 46 | #define INSTALL_FT1_SOCKET_SUPPORT FALSE |
| 47 | #define INSTALL_AM3_SOCKET_SUPPORT FALSE |
| 48 | |
| 49 | #define INSTALL_FM2_SOCKET_SUPPORT FALSE |
| 50 | |
| 51 | //#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE |
| 52 | //#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE |
| 53 | #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE |
| 54 | //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE |
| 55 | //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE |
| 56 | //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE |
| 57 | #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE |
| 58 | #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE |
| 59 | #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE |
| 60 | //#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE |
| 61 | #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE |
| 62 | //#define BLDOPT_REMOVE_ACPI_PSTATES FALSE |
| 63 | #define BLDOPT_REMOVE_SRAT FALSE //TRUE |
| 64 | #define BLDOPT_REMOVE_SLIT FALSE //TRUE |
| 65 | #define BLDOPT_REMOVE_WHEA FALSE //TRUE |
| 66 | #define BLDOPT_REMOVE_CRAT TRUE |
WANG Siyuan | 87bdd86 | 2013-11-18 10:34:06 +0800 | [diff] [blame] | 67 | #define BLDOPT_REMOVE_DMI TRUE |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 68 | //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE |
| 69 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE |
| 70 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE |
| 71 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE |
| 72 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE |
| 73 | //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE |
| 74 | |
| 75 | //This element selects whether P-States should be forced to be independent, |
| 76 | // as reported by the ACPI _PSD object. For single-link processors, |
| 77 | // setting TRUE for OS to support this feature. |
| 78 | |
| 79 | //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE |
| 80 | |
| 81 | #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS |
| 82 | #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER |
| 83 | /* Build configuration values here. |
| 84 | */ |
| 85 | #define BLDCFG_VRM_CURRENT_LIMIT 90000 |
| 86 | #define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 |
| 87 | #define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 |
| 88 | #define BLDCFG_PLAT_NUM_IO_APICS 3 |
| 89 | #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST |
| 90 | #define BLDCFG_MEM_INIT_PSTATE 0 |
| 91 | |
| 92 | #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE |
| 93 | |
| 94 | #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY |
| 95 | #define BLDCFG_MEMORY_MODE_UNGANGED TRUE |
| 96 | #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE |
| 97 | #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| 98 | #define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE |
| 99 | #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE |
| 100 | #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE |
| 101 | #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE |
| 102 | #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE |
| 103 | #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE |
| 104 | #define BLDCFG_MEMORY_POWER_DOWN TRUE |
| 105 | #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT |
| 106 | #define BLDCFG_ONLINE_SPARE FALSE |
| 107 | #define BLDCFG_BANK_SWIZZLE TRUE |
| 108 | #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO |
| 109 | #define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY |
| 110 | #define BLDCFG_DQS_TRAINING_CONTROL TRUE |
| 111 | #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE |
| 112 | #define BLDCFG_USE_BURST_MODE FALSE |
| 113 | #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE |
| 114 | #define BLDCFG_ENABLE_ECC_FEATURE TRUE |
| 115 | #define BLDCFG_ECC_REDIRECTION FALSE |
| 116 | #define BLDCFG_SCRUB_DRAM_RATE 0 |
| 117 | #define BLDCFG_SCRUB_L2_RATE 0 |
| 118 | #define BLDCFG_SCRUB_L3_RATE 0 |
| 119 | #define BLDCFG_SCRUB_IC_RATE 0 |
| 120 | #define BLDCFG_SCRUB_DC_RATE 0 |
| 121 | #define BLDCFG_ECC_SYMBOL_SIZE 4 |
| 122 | #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 |
| 123 | #define BLDCFG_ECC_SYNC_FLOOD FALSE |
| 124 | #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE |
| 125 | #define BLDCFG_1GB_ALIGN FALSE |
| 126 | #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE |
| 127 | #define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% |
| 128 | #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 |
| 129 | |
| 130 | #define BLDOPT_REMOVE_ALIB FALSE |
| 131 | #define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled |
| 132 | #define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' |
| 133 | #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' |
| 134 | #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 |
| 135 | |
| 136 | #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 |
| 137 | #define BLDCFG_CFG_ABM_SUPPORT 0 |
| 138 | |
| 139 | //#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 |
| 140 | |
| 141 | // Specify the default values for the VRM controlling the VDDNB plane. |
| 142 | // If not specified, the values used for the core VRM will be applied |
| 143 | //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity |
| 144 | //#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L |
| 145 | //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime |
| 146 | //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity |
| 147 | //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity |
| 148 | //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity |
| 149 | |
| 150 | #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 |
| 151 | |
| 152 | #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 |
| 153 | #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 |
| 154 | |
Martin Roth | f95911a | 2017-06-24 21:45:13 -0600 | [diff] [blame] | 155 | #if IS_ENABLED(CONFIG_GFXUMA) |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 156 | #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED |
| 157 | #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED |
| 158 | //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ |
| 159 | #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M |
| 160 | #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE |
| 161 | #endif |
| 162 | |
| 163 | #define BLDCFG_IOMMU_SUPPORT FALSE |
| 164 | |
| 165 | #define BLDCFG_CFG_GNB_HD_AUDIO TRUE |
| 166 | //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID |
| 167 | //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID |
| 168 | //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID |
| 169 | |
| 170 | /* Process the options... |
| 171 | * This file include MUST occur AFTER the user option selection settings |
| 172 | */ |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 173 | /* |
| 174 | * Customized OEM build configurations for FCH component |
| 175 | */ |
| 176 | // #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 |
| 177 | // #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 |
| 178 | // #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 |
| 179 | // #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 |
| 180 | // #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 |
| 181 | // #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 |
| 182 | // #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 |
| 183 | // #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 |
| 184 | // #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 |
| 185 | // #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 |
| 186 | // #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 |
| 187 | // #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 |
| 188 | // #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 |
| 189 | // #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 |
| 190 | // #define BLDCFG_AZALIA_SSID 0x780D1022 |
| 191 | // #define BLDCFG_SMBUS_SSID 0x780B1022 |
| 192 | // #define BLDCFG_IDE_SSID 0x780C1022 |
| 193 | // #define BLDCFG_SATA_AHCI_SSID 0x78011022 |
| 194 | // #define BLDCFG_SATA_IDE_SSID 0x78001022 |
| 195 | // #define BLDCFG_SATA_RAID5_SSID 0x78031022 |
| 196 | // #define BLDCFG_SATA_RAID_SSID 0x78021022 |
| 197 | // #define BLDCFG_EHCI_SSID 0x78081022 |
| 198 | // #define BLDCFG_OHCI_SSID 0x78071022 |
| 199 | // #define BLDCFG_LPC_SSID 0x780E1022 |
| 200 | // #define BLDCFG_SD_SSID 0x78061022 |
| 201 | // #define BLDCFG_XHCI_SSID 0x78121022 |
| 202 | // #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE |
| 203 | // #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE |
| 204 | // #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 |
| 205 | // #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE |
| 206 | // #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE |
| 207 | // #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE |
| 208 | // #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE |
| 209 | // #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE |
| 210 | // #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE |
| 211 | // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE |
| 212 | // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE |
| 213 | |
| 214 | CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = |
| 215 | { |
| 216 | { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, |
| 217 | { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, |
| 218 | { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, |
| 219 | { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, |
| 220 | { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, |
| 221 | { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, |
| 222 | { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, |
| 223 | { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, |
| 224 | { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, |
| 225 | { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, |
| 226 | { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, |
| 227 | { CPU_LIST_TERMINAL } |
| 228 | }; |
| 229 | |
| 230 | #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList |
| 231 | |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 232 | |
| 233 | /* Include the files that instantiate the configuration definitions. */ |
| 234 | #include "cpuRegisters.h" |
| 235 | #include "cpuFamRegisters.h" |
| 236 | #include "cpuFamilyTranslation.h" |
| 237 | #include "AdvancedApi.h" |
| 238 | #include "heapManager.h" |
| 239 | #include "CreateStruct.h" |
| 240 | #include "cpuFeatures.h" |
| 241 | #include "Table.h" |
zbao | ea71e81 | 2012-08-02 18:36:36 +0800 | [diff] [blame] | 242 | #include "cpuEarlyInit.h" |
| 243 | #include "cpuLateInit.h" |
| 244 | #include "GnbInterface.h" |
| 245 | |
| 246 | // This is the delivery package title, "BrazosPI" |
| 247 | // This string MUST be exactly 8 characters long |
| 248 | #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} |
| 249 | |
| 250 | // This is the release version number of the AGESA component |
| 251 | // This string MUST be exactly 12 characters long |
| 252 | #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} |
| 253 | |
| 254 | /* MEMORY_BUS_SPEED */ |
| 255 | #define DDR400_FREQUENCY 200 ///< DDR 400 |
| 256 | #define DDR533_FREQUENCY 266 ///< DDR 533 |
| 257 | #define DDR667_FREQUENCY 333 ///< DDR 667 |
| 258 | #define DDR800_FREQUENCY 400 ///< DDR 800 |
| 259 | #define DDR1066_FREQUENCY 533 ///< DDR 1066 |
| 260 | #define DDR1333_FREQUENCY 667 ///< DDR 1333 |
| 261 | #define DDR1600_FREQUENCY 800 ///< DDR 1600 |
| 262 | #define DDR1866_FREQUENCY 933 ///< DDR 1866 |
| 263 | #define DDR2100_FREQUENCY 1050 ///< DDR 2100 |
| 264 | #define DDR2133_FREQUENCY 1066 ///< DDR 2133 |
| 265 | #define DDR2400_FREQUENCY 1200 ///< DDR 2400 |
| 266 | #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency |
| 267 | |
| 268 | /* QUANDRANK_TYPE*/ |
| 269 | #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM |
| 270 | #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM |
| 271 | |
| 272 | /* USER_MEMORY_TIMING_MODE */ |
| 273 | #define TIMING_MODE_AUTO 0 ///< Use best rate possible |
| 274 | #define TIMING_MODE_LIMITED 1 ///< Set user top limit |
| 275 | #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed |
| 276 | |
| 277 | /* POWER_DOWN_MODE */ |
| 278 | #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode |
| 279 | #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode |
| 280 | |
| 281 | /* |
| 282 | * Agesa optional capabilities selection. |
| 283 | * Uncomment and mark FALSE those features you wish to include in the build. |
| 284 | * Comment out or mark TRUE those features you want to REMOVE from the build. |
| 285 | */ |
| 286 | |
| 287 | #define DFLT_SMBUS0_BASE_ADDRESS 0xB00 |
| 288 | #define DFLT_SMBUS1_BASE_ADDRESS 0xB20 |
| 289 | #define DFLT_SIO_PME_BASE_ADDRESS 0xE00 |
| 290 | #define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 |
| 291 | #define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 |
| 292 | #define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 |
| 293 | #define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 |
| 294 | #define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 |
| 295 | #define DFLT_SPI_BASE_ADDRESS 0xFEC10000 |
| 296 | #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 |
| 297 | #define DFLT_HPET_BASE_ADDRESS 0xFED00000 |
| 298 | #define DFLT_SMI_CMD_PORT 0xB0 |
| 299 | #define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 |
| 300 | #define DFLT_GEC_BASE_ADDRESS 0xFED61000 |
| 301 | #define DFLT_AZALIA_SSID 0x780D1022 |
| 302 | #define DFLT_SMBUS_SSID 0x780B1022 |
| 303 | #define DFLT_IDE_SSID 0x780C1022 |
| 304 | #define DFLT_SATA_AHCI_SSID 0x78011022 |
| 305 | #define DFLT_SATA_IDE_SSID 0x78001022 |
| 306 | #define DFLT_SATA_RAID5_SSID 0x78031022 |
| 307 | #define DFLT_SATA_RAID_SSID 0x78021022 |
| 308 | #define DFLT_EHCI_SSID 0x78081022 |
| 309 | #define DFLT_OHCI_SSID 0x78071022 |
| 310 | #define DFLT_LPC_SSID 0x780E1022 |
| 311 | #define DFLT_SD_SSID 0x78061022 |
| 312 | #define DFLT_XHCI_SSID 0x78121022 |
| 313 | #define DFLT_FCH_PORT80_BEHIND_PCIB FALSE |
| 314 | #define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE |
| 315 | #define DFLT_FCH_GPP_LINK_CONFIG PortA4 |
| 316 | #define DFLT_FCH_GPP_PORT0_PRESENT FALSE |
| 317 | #define DFLT_FCH_GPP_PORT1_PRESENT FALSE |
| 318 | #define DFLT_FCH_GPP_PORT2_PRESENT FALSE |
| 319 | #define DFLT_FCH_GPP_PORT3_PRESENT FALSE |
| 320 | #define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE |
| 321 | #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE |
| 322 | #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE |
| 323 | #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE |
| 324 | //#define BLDCFG_IR_PIN_CONTROL 0x33 |
| 325 | #define FCH_NO_XHCI_SUPPORT TRUE |
| 326 | GPIO_CONTROL thatcher_gpio[] = { |
| 327 | {183, Function1, PullUpB}, |
| 328 | {-1} |
| 329 | }; |
| 330 | #define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0]) |
| 331 | |
| 332 | // The following definitions specify the default values for various parameters in which there are |
| 333 | // no clearly defined defaults to be used in the common file. The values below are based on product |
| 334 | // and BKDG content, please consult the AGESA Memory team for consultation. |
| 335 | #define DFLT_SCRUB_DRAM_RATE (0) |
| 336 | #define DFLT_SCRUB_L2_RATE (0) |
| 337 | #define DFLT_SCRUB_L3_RATE (0) |
| 338 | #define DFLT_SCRUB_IC_RATE (0) |
| 339 | #define DFLT_SCRUB_DC_RATE (0) |
| 340 | #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| 341 | #define DFLT_VRM_SLEW_RATE (5000) |
| 342 | |
Kyösti Mälkki | c8e4742 | 2017-08-31 08:52:12 +0300 | [diff] [blame] | 343 | #include <PlatformInstall.h> |