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Arthur Heymansfc31e442018-02-12 15:12:34 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#ifndef DEVICE_DRAM_COMMON_H
19#define DEVICE_DRAM_COMMON_H
20
21/**
22 * \brief Convenience definitions for TCK values
23 *
24 * Different values for tCK, representing standard DDR3 frequencies.
25 * These values are in 1/256 ns units.
26 * @{
27 */
28#define NS2MHZ_DIV256 (1000 << 8)
29
30#define TCK_1333MHZ 192
31#define TCK_1200MHZ 212
32#define TCK_1100MHZ 232
33#define TCK_1066MHZ 240
34#define TCK_1000MHZ 256
35#define TCK_933MHZ 274
36#define TCK_900MHZ 284
37#define TCK_800MHZ 320
38#define TCK_700MHZ 365
39#define TCK_666MHZ 384
40#define TCK_533MHZ 480
41#define TCK_400MHZ 640
42#define TCK_333MHZ 768
43#define TCK_266MHZ 960
44#define TCK_200MHZ 1280
45/** @} */
46
47/**
48 * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP
49 *
50 * Use this macro instead of printk(); for verbose RAM initialization messages.
51 * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically
52 * disabled.
53 * @{
54 */
55#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
56#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
57#else
58#define printram(x, ...)
59#endif
60/** @} */
61
62/** Result of the SPD decoding process */
63enum spd_status {
64 SPD_STATUS_OK = 0,
65 SPD_STATUS_INVALID,
66 SPD_STATUS_CRC_ERROR,
67 SPD_STATUS_INVALID_FIELD,
68};
69
Arthur Heymans97b337b2018-01-22 01:26:53 +010070u16 ddr3_crc16(const u8 *ptr, int n_crc);
71
Arthur Heymansfc31e442018-02-12 15:12:34 +010072#endif /* DEVICE_DRAM_COMMON_H */