Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2007-2008 coresystems GmbH |
| 6 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 7 | * Copyright (C) 2015 Intel Corp. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <cpu/x86/mtrr.h> |
| 20 | #include <cpu/x86/cache.h> |
| 21 | #include <cpu/x86/post_code.h> |
| 22 | |
| 23 | /* |
| 24 | * This is the common entry point after DRAM has been initialized. |
| 25 | */ |
| 26 | /* |
| 27 | * eax: New stack address |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 28 | */ |
| 29 | |
| 30 | /* Switch to the stack in RAM */ |
| 31 | movl %eax, %esp |
| 32 | |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 33 | #if IS_ENABLED(CONFIG_SKIP_FSP_CAR) |
| 34 | |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 35 | /* chipset_teardown_car() is expected to disable cache-as-ram. */ |
| 36 | call chipset_teardown_car |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 37 | |
| 38 | #else |
| 39 | .extern fih_car |
| 40 | |
Duncan Laurie | fb50983 | 2015-11-22 14:53:57 -0800 | [diff] [blame] | 41 | post_code(POST_FSP_TEMP_RAM_EXIT) |
| 42 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 43 | /* Calculate TempRamExit entry into FSP */ |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 44 | movl fih_car, %ebp |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 45 | mov 0x40(%ebp), %eax |
| 46 | add 0x1c(%ebp), %eax |
| 47 | |
| 48 | /* Build the call frame */ |
| 49 | pushl $0 |
| 50 | |
| 51 | /* Call TempRamExit */ |
| 52 | call *%eax |
| 53 | add $4, %esp |
| 54 | cmp $0, %eax |
| 55 | jz 1f |
| 56 | /* |
| 57 | * Failures for post code BC - failed in TempRamExit |
| 58 | * |
| 59 | * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully. |
| 60 | * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. |
| 61 | * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. |
| 62 | * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed. |
| 63 | */ |
| 64 | movb $0xBC, %ah |
| 65 | jmp .Lhlt |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 66 | 1: |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 67 | #endif |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 68 | /* Display the MTRRs */ |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 69 | call display_mtrrs |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 70 | |
| 71 | /* |
| 72 | * The stack contents are initialized in src/soc/intel/common/stack.c |
| 73 | * to be the following: |
| 74 | * |
| 75 | * * |
| 76 | * * |
| 77 | * * |
| 78 | * +36: MTRR mask 1 63:32 |
| 79 | * +32: MTRR mask 1 31:0 |
| 80 | * +28: MTRR base 1 63:32 |
| 81 | * +24: MTRR base 1 31:0 |
| 82 | * +20: MTRR mask 0 63:32 |
| 83 | * +16: MTRR mask 0 31:0 |
| 84 | * +12: MTRR base 0 63:32 |
| 85 | * +8: MTRR base 0 31:0 |
| 86 | * +4: Number of MTRRs to setup (described above) |
| 87 | * +0: Number of variable MTRRs to clear |
| 88 | */ |
| 89 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 90 | #if IS_ENABLED(CONFIG_SOC_SETS_MSRS) |
Lee Leahy | 9590992 | 2016-01-29 14:35:13 -0800 | [diff] [blame] | 91 | push %esp |
| 92 | call soc_set_mtrrs |
| 93 | |
| 94 | /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ |
| 95 | movl %eax, %esp |
| 96 | #else |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 97 | /* Clear all of the variable MTRRs. */ |
| 98 | popl %ebx |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 99 | movl $MTRR_PHYS_BASE(0), %ecx |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 100 | clr %eax |
| 101 | clr %edx |
| 102 | |
| 103 | 1: |
| 104 | testl %ebx, %ebx |
| 105 | jz 1f |
| 106 | wrmsr /* Write MTRR base. */ |
| 107 | inc %ecx |
| 108 | wrmsr /* Write MTRR mask. */ |
| 109 | inc %ecx |
| 110 | dec %ebx |
| 111 | jmp 1b |
| 112 | |
| 113 | 1: |
| 114 | /* Get number of MTRRs. */ |
| 115 | popl %ebx |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 116 | movl $MTRR_PHYS_BASE(0), %ecx |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 117 | 2: |
| 118 | testl %ebx, %ebx |
| 119 | jz 2f |
| 120 | |
| 121 | /* Low 32 bits of MTRR base. */ |
| 122 | popl %eax |
| 123 | /* Upper 32 bits of MTRR base. */ |
| 124 | popl %edx |
| 125 | /* Write MTRR base. */ |
| 126 | wrmsr |
| 127 | inc %ecx |
| 128 | /* Low 32 bits of MTRR mask. */ |
| 129 | popl %eax |
| 130 | /* Upper 32 bits of MTRR mask. */ |
| 131 | popl %edx |
| 132 | /* Write MTRR mask. */ |
| 133 | wrmsr |
| 134 | inc %ecx |
| 135 | |
| 136 | dec %ebx |
| 137 | jmp 2b |
| 138 | 2: |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 139 | #endif /* CONFIG_SOC_SETS_MSRS */ |
Lee Leahy | 9590992 | 2016-01-29 14:35:13 -0800 | [diff] [blame] | 140 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 141 | post_code(0x39) |
| 142 | |
| 143 | /* And enable cache again after setting MTRRs. */ |
| 144 | movl %cr0, %eax |
| 145 | andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax |
| 146 | movl %eax, %cr0 |
| 147 | |
| 148 | post_code(0x3a) |
| 149 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 150 | #if IS_ENABLED(CONFIG_SOC_SETS_MSRS) |
Lee Leahy | 9590992 | 2016-01-29 14:35:13 -0800 | [diff] [blame] | 151 | call soc_enable_mtrrs |
| 152 | #else |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 153 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 154 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 155 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 156 | orl $MTRR_DEF_TYPE_EN, %eax |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 157 | wrmsr |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 158 | #endif /* CONFIG_SOC_SETS_MSRS */ |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 159 | |
| 160 | post_code(0x3b) |
| 161 | |
| 162 | /* Invalidate the cache again. */ |
| 163 | invd |
| 164 | |
| 165 | post_code(0x3c) |
| 166 | |
| 167 | __main: |
| 168 | post_code(POST_PREPARE_RAMSTAGE) |
| 169 | cld /* Clear direction flag. */ |
| 170 | call after_cache_as_ram |