Arthur Heymans | 6336d4c | 2018-01-25 21:38:25 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * 2012 secunet Security Networks AG |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <cpu/x86/mtrr.h> |
| 20 | #include <cpu/x86/mp.h> |
| 21 | #include <cpu/intel/microcode.h> |
| 22 | #include <cpu/intel/smm/gen1/smi.h> |
| 23 | #include <cpu/intel/common/common.h> |
| 24 | |
| 25 | /* Parallel MP initialization support. */ |
| 26 | static const void *microcode_patch; |
| 27 | |
| 28 | static void pre_mp_init(void) |
| 29 | { |
Nico Huber | 2d0fe4f | 2019-02-28 22:57:16 +0100 | [diff] [blame] | 30 | intel_microcode_load_unlocked(microcode_patch); |
| 31 | |
Arthur Heymans | 6336d4c | 2018-01-25 21:38:25 +0100 | [diff] [blame] | 32 | /* Setup MTRRs based on physical address size. */ |
| 33 | x86_setup_mtrrs_with_detect(); |
| 34 | x86_mtrr_check(); |
| 35 | } |
| 36 | |
| 37 | static int get_cpu_count(void) |
| 38 | { |
| 39 | const struct cpuid_result cpuid1 = cpuid(1); |
| 40 | const char cores = (cpuid1.ebx >> 16) & 0xf; |
| 41 | |
| 42 | printk(BIOS_DEBUG, "CPU has %u cores.\n", cores); |
| 43 | |
| 44 | return cores; |
| 45 | } |
| 46 | |
Nico Huber | 2d0fe4f | 2019-02-28 22:57:16 +0100 | [diff] [blame] | 47 | static void get_microcode_info(const void **microcode, int *parallel) |
| 48 | { |
| 49 | *microcode = microcode_patch; |
| 50 | *parallel = 1; |
| 51 | } |
| 52 | |
Arthur Heymans | 6336d4c | 2018-01-25 21:38:25 +0100 | [diff] [blame] | 53 | /* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL |
| 54 | to enable SMRR so configure IA32_FEATURE_CONTROL early on */ |
| 55 | static void pre_mp_smm_init(void) |
| 56 | { |
| 57 | smm_initialize(); |
| 58 | } |
| 59 | |
Arthur Heymans | df7aecd | 2018-07-21 15:03:06 +0200 | [diff] [blame] | 60 | #define SMRR_SUPPORTED (1 << 11) |
| 61 | |
Arthur Heymans | 6336d4c | 2018-01-25 21:38:25 +0100 | [diff] [blame] | 62 | static void per_cpu_smm_trigger(void) |
| 63 | { |
Arthur Heymans | df7aecd | 2018-07-21 15:03:06 +0200 | [diff] [blame] | 64 | msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); |
| 65 | if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) { |
| 66 | set_feature_ctrl_vmx(); |
| 67 | msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); |
| 68 | /* We don't care if the lock is already setting |
| 69 | as our smm relocation handler is able to handle |
| 70 | setups where SMRR is not enabled here. */ |
Arthur Heymans | 6671081 | 2019-02-06 13:47:58 +0100 | [diff] [blame] | 71 | if (ia32_ft_ctrl.lo & (1 << 0)) { |
| 72 | /* IA32_FEATURE_CONTROL locked. If we set it again we |
| 73 | get an illegal instruction. */ |
| 74 | printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n"); |
| 75 | printk(BIOS_DEBUG, "SMRR status: %senabled\n", |
| 76 | ia32_ft_ctrl.lo & (1 << 3) ? "" : "not "); |
| 77 | } else { |
| 78 | if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT)) |
| 79 | printk(BIOS_INFO, |
| 80 | "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n"); |
| 81 | ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); |
| 82 | wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); |
| 83 | } |
Arthur Heymans | df7aecd | 2018-07-21 15:03:06 +0200 | [diff] [blame] | 84 | } else { |
| 85 | set_vmx_and_lock(); |
| 86 | } |
| 87 | |
Arthur Heymans | 6336d4c | 2018-01-25 21:38:25 +0100 | [diff] [blame] | 88 | /* Relocate the SMM handler. */ |
| 89 | smm_relocate(); |
Arthur Heymans | 6336d4c | 2018-01-25 21:38:25 +0100 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | static void post_mp_init(void) |
| 93 | { |
| 94 | /* Now that all APs have been relocated as well as the BSP let SMIs |
| 95 | * start flowing. */ |
| 96 | southbridge_smm_init(); |
| 97 | |
| 98 | /* Lock down the SMRAM space. */ |
| 99 | smm_lock(); |
| 100 | } |
| 101 | |
| 102 | static const struct mp_ops mp_ops = { |
| 103 | .pre_mp_init = pre_mp_init, |
| 104 | .get_cpu_count = get_cpu_count, |
| 105 | .get_smm_info = smm_info, |
Nico Huber | 2d0fe4f | 2019-02-28 22:57:16 +0100 | [diff] [blame] | 106 | .get_microcode_info = get_microcode_info, |
Arthur Heymans | 6336d4c | 2018-01-25 21:38:25 +0100 | [diff] [blame] | 107 | .pre_mp_smm_init = pre_mp_smm_init, |
| 108 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 109 | .relocation_handler = smm_relocation_handler, |
| 110 | .post_mp_init = post_mp_init, |
| 111 | }; |
| 112 | |
| 113 | void bsp_init_and_start_aps(struct bus *cpu_bus) |
| 114 | { |
Nico Huber | 2d0fe4f | 2019-02-28 22:57:16 +0100 | [diff] [blame] | 115 | microcode_patch = intel_microcode_find(); |
| 116 | |
Arthur Heymans | 6336d4c | 2018-01-25 21:38:25 +0100 | [diff] [blame] | 117 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| 118 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 119 | } |