Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <cpu/x86/mtrr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 17 | #include <cpu/amd/msr.h> |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 18 | #include <cpu/amd/mtrr.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 19 | #include <northbridge/amd/agesa/agesa_helper.h> |
Kyösti Mälkki | 4286502 | 2017-09-28 16:42:41 +0300 | [diff] [blame] | 20 | #include <Porting.h> |
| 21 | #include <AGESA.h> |
| 22 | #include <amdlib.h> |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 23 | |
| 24 | void amd_initcpuio(void) |
| 25 | { |
| 26 | UINT64 MsrReg; |
| 27 | UINT32 PciData; |
| 28 | PCI_ADDR PciAddress; |
| 29 | AMD_CONFIG_PARAMS StdHeader; |
| 30 | |
| 31 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 32 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 33 | PciData = 1; |
| 34 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 35 | |
| 36 | /* The platform BIOS needs to ensure the memory ranges of SB800 legacy |
| 37 | * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are |
| 38 | * set to non-posted regions. |
| 39 | */ |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 40 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); |
| 41 | /* last address before processor local APIC at FEE00000 */ |
| 42 | PciData = 0x00FEDF00; |
| 43 | /* set NP (non-posted) bit */ |
| 44 | PciData |= 1 << 7; |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 45 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 46 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); |
| 47 | /* lowest NP address is HPET at FED00000 */ |
| 48 | PciData = (0xFED00000 >> 8) | 3; |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 49 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 50 | |
| 51 | /* Map the remaining PCI hole as posted MMIO */ |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 52 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 53 | PciData = 0x00FECF00; /* last address before non-posted range */ |
| 54 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 55 | LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 56 | MsrReg = (MsrReg >> 8) | 3; |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 57 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 58 | PciData = (UINT32)MsrReg; |
| 59 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 60 | |
| 61 | /* Send all IO (0000-FFFF) to southbridge. */ |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 62 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 63 | PciData = 0x0000F000; |
| 64 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 65 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 66 | PciData = 0x00000003; |
| 67 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 68 | } |
| 69 | |
| 70 | void amd_initmmio(void) |
| 71 | { |
| 72 | UINT64 MsrReg; |
| 73 | UINT32 PciData; |
| 74 | PCI_ADDR PciAddress; |
| 75 | AMD_CONFIG_PARAMS StdHeader; |
| 76 | |
| 77 | /* |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 78 | * Set the MMIO Configuration Base Address and |
| 79 | * Bus Range onto MMIO configuration base |
| 80 | * Address MSR register. |
| 81 | */ |
| 82 | MsrReg = CONFIG_MMCONF_BASE_ADDRESS | |
| 83 | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 84 | LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 85 | |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 86 | /* For serial port */ |
| 87 | PciData = 0xFF03FFD5; |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 88 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 89 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 90 | |
| 91 | /* PSP */ |
| 92 | //PciData = 0xD; |
| 93 | //PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x8, 0x0, 0x48); |
| 94 | //LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 95 | |
| 96 | /* Set ROM cache onto WP to decrease post time */ |
| 97 | MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 98 | LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 99 | MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 100 | LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); |
Marshall Dawson | 03e6a45 | 2017-02-12 10:31:15 -0700 | [diff] [blame] | 101 | |
Evelyn Huang | 0182aea2 | 2017-06-07 14:20:09 -0600 | [diff] [blame] | 102 | if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { |
Marshall Dawson | 03e6a45 | 2017-02-12 10:31:15 -0700 | [diff] [blame] | 103 | LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); |
| 104 | MsrReg |= 1 << 11; |
| 105 | LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); |
| 106 | } |
Dave Frodin | 4b45dd3 | 2015-03-13 09:29:20 -0600 | [diff] [blame] | 107 | } |