Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 18 | #include <cpu/amd/msr.h> |
| 19 | #include <cpu/x86/mtrr.h> |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 20 | #include <cpu/amd/mtrr.h> |
| 21 | #include <device/device.h> |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 22 | #include <string.h> |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 23 | #include <cpu/x86/pae.h> |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 24 | #include <cpu/x86/lapic.h> |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 25 | #include <cpu/cpu.h> |
| 26 | #include <cpu/x86/cache.h> |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 27 | #include <arch/acpi.h> |
Kyösti Mälkki | d4955f0 | 2017-09-08 07:14:17 +0300 | [diff] [blame] | 28 | #include <northbridge/amd/agesa/agesa_helper.h> |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 29 | |
Elyes HAOUAS | d2d8a31 | 2018-02-08 13:38:21 +0100 | [diff] [blame] | 30 | static void model_16_init(struct device *dev) |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 31 | { |
| 32 | printk(BIOS_DEBUG, "Model 16 Init.\n"); |
| 33 | |
| 34 | u8 i; |
| 35 | msr_t msr; |
Marshall Dawson | bd4a3f8 | 2018-08-07 07:27:57 -0600 | [diff] [blame] | 36 | int num_banks; |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 37 | int msrno; |
Edward O'Callaghan | 3b8bfeb | 2014-11-21 12:34:00 +1100 | [diff] [blame] | 38 | #if IS_ENABLED(CONFIG_LOGICAL_CPUS) |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 39 | u32 siblings; |
| 40 | #endif |
| 41 | |
| 42 | //x86_enable_cache(); |
| 43 | //amd_setup_mtrrs(); |
| 44 | //x86_mtrr_check(); |
Elyes HAOUAS | 12d65f8 | 2018-01-28 22:35:47 +0100 | [diff] [blame] | 45 | disable_cache(); |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 46 | /* Enable access to AMD RdDram and WrDram extension bits */ |
| 47 | msr = rdmsr(SYSCFG_MSR); |
| 48 | msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 49 | msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; |
| 50 | wrmsr(SYSCFG_MSR, msr); |
| 51 | |
| 52 | // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs |
| 53 | msr.lo = msr.hi = 0; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 54 | wrmsr(MTRR_FIX_16K_A0000, msr); |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 55 | msr.lo = msr.hi = 0x1e1e1e1e; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 56 | wrmsr(MTRR_FIX_64K_00000, msr); |
| 57 | wrmsr(MTRR_FIX_16K_80000, msr); |
| 58 | for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) |
| 59 | wrmsr(msrno, msr); |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 60 | |
| 61 | msr = rdmsr(SYSCFG_MSR); |
| 62 | msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 63 | msr.lo |= SYSCFG_MSR_MtrrFixDramEn; |
| 64 | wrmsr(SYSCFG_MSR, msr); |
| 65 | |
Kyösti Mälkki | 9107e53 | 2014-06-19 20:52:39 +0300 | [diff] [blame] | 66 | if (acpi_is_wakeup()) |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 67 | restore_mtrr(); |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 68 | |
| 69 | x86_mtrr_check(); |
| 70 | x86_enable_cache(); |
| 71 | |
| 72 | /* zero the machine check error status registers */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 73 | msr = rdmsr(IA32_MCG_CAP); |
Marshall Dawson | bd4a3f8 | 2018-08-07 07:27:57 -0600 | [diff] [blame] | 74 | num_banks = msr.lo & MCA_BANKS_MASK; |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 75 | msr.lo = 0; |
| 76 | msr.hi = 0; |
Marshall Dawson | bd4a3f8 | 2018-08-07 07:27:57 -0600 | [diff] [blame] | 77 | for (i = 0; i < num_banks; i++) |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 78 | wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 79 | |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 80 | /* Enable the local CPU APICs */ |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 81 | setup_lapic(); |
| 82 | |
Edward O'Callaghan | 3b8bfeb | 2014-11-21 12:34:00 +1100 | [diff] [blame] | 83 | #if IS_ENABLED(CONFIG_LOGICAL_CPUS) |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 84 | siblings = cpuid_ecx(0x80000008) & 0xff; |
| 85 | |
| 86 | if (siblings > 0) { |
| 87 | msr = rdmsr_amd(CPU_ID_FEATURES_MSR); |
| 88 | msr.lo |= 1 << 28; |
| 89 | wrmsr_amd(CPU_ID_FEATURES_MSR, msr); |
| 90 | |
| 91 | msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); |
| 92 | msr.hi |= 1 << (33 - 32); |
| 93 | wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); |
| 94 | } |
| 95 | printk(BIOS_DEBUG, "siblings = %02d, ", siblings); |
| 96 | #endif |
| 97 | |
| 98 | /* DisableCf8ExtCfg */ |
| 99 | msr = rdmsr(NB_CFG_MSR); |
| 100 | msr.hi &= ~(1 << (46 - 32)); |
| 101 | wrmsr(NB_CFG_MSR, msr); |
| 102 | |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 103 | /* Write protect SMM space with SMMLOCK. */ |
| 104 | msr = rdmsr(HWCR_MSR); |
| 105 | msr.lo |= (1 << 0); |
| 106 | wrmsr(HWCR_MSR, msr); |
| 107 | } |
| 108 | |
| 109 | static struct device_operations cpu_dev_ops = { |
| 110 | .init = model_16_init, |
| 111 | }; |
| 112 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 113 | static const struct cpu_device_id cpu_table[] = { |
Paul Menzel | 22f32c7 | 2017-02-27 01:26:42 +0100 | [diff] [blame] | 114 | { X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */ |
Siyuan Wang | 5d7d09c | 2013-07-09 17:08:41 +0800 | [diff] [blame] | 115 | { 0, 0 }, |
| 116 | }; |
| 117 | |
| 118 | static const struct cpu_driver model_15 __cpu_driver = { |
| 119 | .ops = &cpu_dev_ops, |
| 120 | .id_table = cpu_table, |
| 121 | }; |