Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 18 | #include <cpu/amd/msr.h> |
| 19 | #include <cpu/x86/mtrr.h> |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 20 | #include <cpu/amd/mtrr.h> |
| 21 | #include <device/device.h> |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 22 | #include <string.h> |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 23 | #include <cpu/x86/pae.h> |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 24 | #include <cpu/x86/lapic.h> |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 25 | #include <cpu/cpu.h> |
| 26 | #include <cpu/x86/cache.h> |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 27 | #include <arch/acpi.h> |
Kyösti Mälkki | d4955f0 | 2017-09-08 07:14:17 +0300 | [diff] [blame] | 28 | #include <northbridge/amd/agesa/agesa_helper.h> |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 29 | |
Elyes HAOUAS | d2d8a31 | 2018-02-08 13:38:21 +0100 | [diff] [blame] | 30 | static void model_14_init(struct device *dev) |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 31 | { |
Paul Menzel | 22f32c7 | 2017-02-27 01:26:42 +0100 | [diff] [blame] | 32 | u8 i; |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 33 | msr_t msr; |
Marshall Dawson | bd4a3f8 | 2018-08-07 07:27:57 -0600 | [diff] [blame] | 34 | int num_banks; |
Paul Menzel | 22f32c7 | 2017-02-27 01:26:42 +0100 | [diff] [blame] | 35 | int msrno; |
Edward O'Callaghan | 3b8bfeb | 2014-11-21 12:34:00 +1100 | [diff] [blame] | 36 | #if IS_ENABLED(CONFIG_LOGICAL_CPUS) |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 37 | u32 siblings; |
| 38 | #endif |
| 39 | printk(BIOS_DEBUG, "Model 14 Init.\n"); |
| 40 | |
Elyes HAOUAS | 12d65f8 | 2018-01-28 22:35:47 +0100 | [diff] [blame] | 41 | disable_cache(); |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 42 | /* |
| 43 | * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set |
| 44 | * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. |
| 45 | * TODO: |
| 46 | * amd_setup_mtrrs(); |
| 47 | */ |
| 48 | |
| 49 | /* Enable access to AMD RdDram and WrDram extension bits */ |
| 50 | msr = rdmsr(SYSCFG_MSR); |
| 51 | msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 52 | msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; |
| 53 | wrmsr(SYSCFG_MSR, msr); |
| 54 | |
| 55 | /* Set shadow WB, RdMEM, WrMEM */ |
| 56 | msr.lo = msr.hi = 0; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 57 | wrmsr(MTRR_FIX_16K_A0000, msr); |
Paul Menzel | 22f32c7 | 2017-02-27 01:26:42 +0100 | [diff] [blame] | 58 | msr.lo = msr.hi = 0x1e1e1e1e; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 59 | wrmsr(MTRR_FIX_64K_00000, msr); |
| 60 | wrmsr(MTRR_FIX_16K_80000, msr); |
| 61 | for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) |
Paul Menzel | 22f32c7 | 2017-02-27 01:26:42 +0100 | [diff] [blame] | 62 | wrmsr(msrno, msr); |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 63 | |
| 64 | msr = rdmsr(SYSCFG_MSR); |
| 65 | msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 66 | msr.lo |= SYSCFG_MSR_MtrrFixDramEn; |
| 67 | wrmsr(SYSCFG_MSR, msr); |
| 68 | |
Kyösti Mälkki | 9107e53 | 2014-06-19 20:52:39 +0300 | [diff] [blame] | 69 | if (acpi_is_wakeup()) |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 70 | restore_mtrr(); |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 71 | |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 72 | x86_mtrr_check(); |
| 73 | x86_enable_cache(); |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 74 | |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 75 | /* zero the machine check error status registers */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 76 | msr = rdmsr(IA32_MCG_CAP); |
Marshall Dawson | bd4a3f8 | 2018-08-07 07:27:57 -0600 | [diff] [blame] | 77 | num_banks = msr.lo & MCA_BANKS_MASK; |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 78 | msr.lo = 0; |
| 79 | msr.hi = 0; |
Marshall Dawson | bd4a3f8 | 2018-08-07 07:27:57 -0600 | [diff] [blame] | 80 | for (i = 0; i < num_banks; i++) |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 81 | wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
Scott Duplichan | a72425a | 2011-05-15 21:01:42 +0000 | [diff] [blame] | 82 | |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 83 | /* Enable the local CPU APICs */ |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 84 | setup_lapic(); |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 85 | |
Edward O'Callaghan | 3b8bfeb | 2014-11-21 12:34:00 +1100 | [diff] [blame] | 86 | #if IS_ENABLED(CONFIG_LOGICAL_CPUS) |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 87 | siblings = cpuid_ecx(0x80000008) & 0xff; |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 88 | |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 89 | if (siblings > 0) { |
| 90 | msr = rdmsr_amd(CPU_ID_FEATURES_MSR); |
| 91 | msr.lo |= 1 << 28; |
| 92 | wrmsr_amd(CPU_ID_FEATURES_MSR, msr); |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 93 | |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 94 | msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); |
| 95 | msr.hi |= 1 << (33 - 32); |
| 96 | wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); |
| 97 | } |
Paul Menzel | 22f32c7 | 2017-02-27 01:26:42 +0100 | [diff] [blame] | 98 | printk(BIOS_DEBUG, "siblings = %02d, ", siblings); |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 99 | #endif |
| 100 | |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 101 | /* DisableCf8ExtCfg */ |
| 102 | msr = rdmsr(NB_CFG_MSR); |
| 103 | msr.hi &= ~(1 << (46 - 32)); |
| 104 | wrmsr(NB_CFG_MSR, msr); |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 105 | |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 106 | /* Write protect SMM space with SMMLOCK. */ |
| 107 | msr = rdmsr(HWCR_MSR); |
| 108 | msr.lo |= (1 << 0); |
| 109 | wrmsr(HWCR_MSR, msr); |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | static struct device_operations cpu_dev_ops = { |
zbao | afd141d | 2012-03-30 15:32:07 +0800 | [diff] [blame] | 113 | .init = model_14_init, |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 114 | }; |
| 115 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 116 | static const struct cpu_device_id cpu_table[] = { |
zbao | afd141d | 2012-03-30 15:32:07 +0800 | [diff] [blame] | 117 | { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ |
| 118 | { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ |
| 119 | { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ |
| 120 | { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ |
| 121 | { 0, 0 }, |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | static const struct cpu_driver model_14 __cpu_driver = { |
zbao | afd141d | 2012-03-30 15:32:07 +0800 | [diff] [blame] | 125 | .ops = &cpu_dev_ops, |
| 126 | .id_table = cpu_table, |
Frank Vibrans | 420faca | 2011-02-14 18:42:12 +0000 | [diff] [blame] | 127 | }; |