blob: c0dcc92bd132b09c19971a371f25286902558737 [file] [log] [blame]
Nico Huber33fcaf92018-10-10 22:44:20 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef X86_CF9_RESET_H
17#define X86_CF9_RESET_H
18
19/* Reset control port */
20#define RST_CNT 0xcf9
21#define FULL_RST (1 << 3)
22#define RST_CPU (1 << 2)
23#define SYS_RST (1 << 1)
24
25/* Implement the bare reset, i.e. write to cf9. */
26void do_system_reset(void);
27void do_full_reset(void);
28
29/* Called by functions below before reset. */
30#if IS_ENABLED(CONFIG_HAVE_CF9_RESET_PREPARE)
31void cf9_reset_prepare(void);
32#else
33static inline void cf9_reset_prepare(void) {}
34#endif
35
36/* Prepare for reset, run do_*_reset(), halt. */
37__noreturn void system_reset(void);
38__noreturn void full_reset(void);
39
40#endif /* X86_CF9_RESET_H */