Aaron Durbin | e581b06 | 2015-09-03 11:29:28 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Andrey Petrov | 73f7069 | 2016-02-28 22:37:15 -0800 | [diff] [blame] | 4 | * Copyright 2016 Google Inc. |
| 5 | * Copyright (C) 2016 Intel Corp. |
Aaron Durbin | e581b06 | 2015-09-03 11:29:28 -0500 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | e581b06 | 2015-09-03 11:29:28 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
Aaron Durbin | aef5865 | 2016-04-29 12:34:01 -0500 | [diff] [blame] | 17 | #include <rules.h> |
Andrey Petrov | 73f7069 | 2016-02-28 22:37:15 -0800 | [diff] [blame] | 18 | |
Aaron Durbin | 0f9af55 | 2018-05-01 14:57:28 -0600 | [diff] [blame] | 19 | #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) |
Aaron Durbin | aef5865 | 2016-04-29 12:34:01 -0500 | [diff] [blame] | 20 | |
| 21 | /* |
| 22 | * This path is for stages that are post bootblock when employing |
Hannah Williams | d3c0c0c | 2018-04-27 09:09:04 -0700 | [diff] [blame] | 23 | * CONFIG_C_ENVIRONMENT_BOOTBLOCK. The gdt is reloaded to accommodate |
| 24 | * platforms that are executing out of CAR. In order to continue with |
| 25 | * C code execution one needs to set stack pointer and clear CAR_GLOBAL |
| 26 | * variables that are stage specific. |
Andrey Petrov | 73f7069 | 2016-02-28 22:37:15 -0800 | [diff] [blame] | 27 | */ |
| 28 | .section ".text._start", "ax", @progbits |
| 29 | .global _start |
| 30 | _start: |
| 31 | |
Hannah Williams | d3c0c0c | 2018-04-27 09:09:04 -0700 | [diff] [blame] | 32 | /* Migrate GDT to this text segment */ |
| 33 | call gdt_init |
| 34 | |
Andrey Petrov | 73f7069 | 2016-02-28 22:37:15 -0800 | [diff] [blame] | 35 | /* reset stack pointer to CAR stack */ |
| 36 | mov $_car_stack_end, %esp |
| 37 | |
| 38 | /* clear CAR_GLOBAL area as it is not shared */ |
| 39 | cld |
| 40 | xor %eax, %eax |
| 41 | movl $(_car_global_end), %ecx |
| 42 | movl $(_car_global_start), %edi |
| 43 | sub %edi, %ecx |
| 44 | rep stosl |
| 45 | |
Lee Leahy | d131ea3 | 2016-06-08 13:40:08 -0700 | [diff] [blame] | 46 | #if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VERSTAGE_DEBUG_SPINLOOP)) \ |
| 47 | || (ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_DEBUG_SPINLOOP))) |
| 48 | |
| 49 | /* Wait for a JTAG debugger to break in and set EBX non-zero */ |
| 50 | xor %ebx, %ebx |
| 51 | |
| 52 | debug_spinloop: |
| 53 | cmp $0, %ebx |
| 54 | jz debug_spinloop |
| 55 | #endif |
| 56 | |
Marshall Dawson | ce9c883 | 2017-07-07 16:09:56 -0600 | [diff] [blame] | 57 | andl $0xfffffff0, %esp |
Aaron Durbin | 4b032e4 | 2018-04-20 01:39:30 -0600 | [diff] [blame] | 58 | #if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) |
| 59 | call exception_init |
| 60 | #endif |
Marshall Dawson | ce9c883 | 2017-07-07 16:09:56 -0600 | [diff] [blame] | 61 | call car_stage_entry |
Andrey Petrov | 73f7069 | 2016-02-28 22:37:15 -0800 | [diff] [blame] | 62 | |
| 63 | /* This is here for linking purposes. */ |
| 64 | .weak car_stage_entry |
| 65 | car_stage_entry: |
| 66 | 1: |
| 67 | jmp 1b |
Aaron Durbin | 800b017 | 2016-04-29 12:10:28 -0500 | [diff] [blame] | 68 | |
| 69 | #else |
| 70 | |
| 71 | /* This file assembles the start of the romstage program by the order of the |
| 72 | * includes. Thus, it's extremely important that one pays very careful |
| 73 | * attention to the order of the includes. */ |
| 74 | |
| 75 | #include <arch/x86/prologue.inc> |
| 76 | #include <cpu/x86/32bit/entry32.inc> |
| 77 | #include <cpu/x86/fpu_enable.inc> |
| 78 | #if IS_ENABLED(CONFIG_SSE) |
| 79 | #include <cpu/x86/sse_enable.inc> |
| 80 | #endif |
| 81 | |
| 82 | /* |
| 83 | * The assembly.inc is generated based on the requirements of the mainboard. |
| 84 | * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be |
| 85 | * processed by ROMCC and added. In non-ROMCC boards the chipsets' |
| 86 | * cache-as-ram setup files would be here. |
| 87 | */ |
| 88 | #include <generated/assembly.inc> |
| 89 | |
Andrey Petrov | 73f7069 | 2016-02-28 22:37:15 -0800 | [diff] [blame] | 90 | #endif |