Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef _CPU_INTEL_HASWELL_H |
| 18 | #define _CPU_INTEL_HASWELL_H |
| 19 | |
Aaron Durbin | 39ecc65 | 2013-05-02 09:42:13 -0500 | [diff] [blame] | 20 | #include <arch/cpu.h> |
| 21 | |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 22 | /* Haswell CPU types */ |
| 23 | #define HASWELL_FAMILY_MOBILE 0x306c0 |
| 24 | #define HASWELL_FAMILY_ULT 0x40650 |
| 25 | |
| 26 | /* Haswell CPU steppings */ |
| 27 | #define HASWELL_STEPPING_MOBILE_A0 1 |
| 28 | #define HASWELL_STEPPING_MOBILE_B0 2 |
| 29 | #define HASWELL_STEPPING_MOBILE_C0 3 |
| 30 | #define HASWELL_STEPPING_MOBILE_D0 4 |
| 31 | #define HASWELL_STEPPING_ULT_B0 0 |
| 32 | #define HASWELL_STEPPING_ULT_C0 1 |
| 33 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | /* Haswell bus clock is fixed at 100MHz */ |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 35 | #define HASWELL_BCLK 100 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | |
Aaron Durbin | a416bfe | 2013-01-12 00:45:10 -0600 | [diff] [blame] | 37 | #define CORE_THREAD_COUNT_MSR 0x35 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | #define IA32_FEATURE_CONTROL 0x3a |
| 39 | #define CPUID_VMX (1 << 5) |
| 40 | #define CPUID_SMX (1 << 6) |
| 41 | #define MSR_FEATURE_CONFIG 0x13c |
| 42 | #define MSR_FLEX_RATIO 0x194 |
| 43 | #define FLEX_RATIO_LOCK (1 << 20) |
| 44 | #define FLEX_RATIO_EN (1 << 16) |
| 45 | #define IA32_PLATFORM_DCA_CAP 0x1f8 |
| 46 | #define IA32_MISC_ENABLE 0x1a0 |
| 47 | #define MSR_TEMPERATURE_TARGET 0x1a2 |
| 48 | #define IA32_PERF_CTL 0x199 |
| 49 | #define IA32_THERM_INTERRUPT 0x19b |
| 50 | #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 |
| 51 | #define ENERGY_POLICY_PERFORMANCE 0 |
| 52 | #define ENERGY_POLICY_NORMAL 6 |
| 53 | #define ENERGY_POLICY_POWERSAVE 15 |
| 54 | #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 |
| 55 | #define MSR_LT_LOCK_MEMORY 0x2e7 |
| 56 | #define IA32_MC0_STATUS 0x401 |
| 57 | |
| 58 | #define MSR_PIC_MSG_CONTROL 0x2e |
| 59 | #define MSR_PLATFORM_INFO 0xce |
| 60 | #define PLATFORM_INFO_SET_TDP (1 << 29) |
| 61 | #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 |
| 62 | #define MSR_PMG_IO_CAPTURE_BASE 0xe4 |
| 63 | |
| 64 | #define MSR_MISC_PWR_MGMT 0x1aa |
| 65 | #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) |
| 66 | #define MSR_TURBO_RATIO_LIMIT 0x1ad |
| 67 | #define MSR_POWER_CTL 0x1fc |
| 68 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 69 | #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a |
| 70 | #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b |
| 71 | #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c |
| 72 | #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 |
| 73 | #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 |
| 74 | #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 75 | #define IRTL_VALID (1 << 15) |
| 76 | #define IRTL_1_NS (0 << 10) |
| 77 | #define IRTL_32_NS (1 << 10) |
| 78 | #define IRTL_1024_NS (2 << 10) |
| 79 | #define IRTL_32768_NS (3 << 10) |
| 80 | #define IRTL_1048576_NS (4 << 10) |
| 81 | #define IRTL_33554432_NS (5 << 10) |
| 82 | #define IRTL_RESPONSE_MASK (0x3ff) |
| 83 | |
| 84 | /* long duration in low dword, short duration in high dword */ |
| 85 | #define MSR_PKG_POWER_LIMIT 0x610 |
| 86 | #define PKG_POWER_LIMIT_MASK 0x7fff |
| 87 | #define PKG_POWER_LIMIT_EN (1 << 15) |
| 88 | #define PKG_POWER_LIMIT_CLAMP (1 << 16) |
| 89 | #define PKG_POWER_LIMIT_TIME_SHIFT 17 |
| 90 | #define PKG_POWER_LIMIT_TIME_MASK 0x7f |
| 91 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 92 | #define MSR_VR_CURRENT_CONFIG 0x601 |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 93 | #define MSR_VR_MISC_CONFIG 0x603 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 94 | #define MSR_PKG_POWER_SKU_UNIT 0x606 |
| 95 | #define MSR_PKG_POWER_SKU 0x614 |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 96 | #define MSR_DDR_RAPL_LIMIT 0x618 |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 97 | #define MSR_VR_MISC_CONFIG2 0x636 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 98 | #define MSR_PP0_POWER_LIMIT 0x638 |
| 99 | #define MSR_PP1_POWER_LIMIT 0x640 |
| 100 | |
| 101 | #define MSR_CONFIG_TDP_NOMINAL 0x648 |
| 102 | #define MSR_CONFIG_TDP_LEVEL1 0x649 |
| 103 | #define MSR_CONFIG_TDP_LEVEL2 0x64a |
| 104 | #define MSR_CONFIG_TDP_CONTROL 0x64b |
| 105 | #define MSR_TURBO_ACTIVATION_RATIO 0x64c |
| 106 | |
| 107 | /* P-state configuration */ |
| 108 | #define PSS_MAX_ENTRIES 8 |
| 109 | #define PSS_RATIO_STEP 2 |
| 110 | #define PSS_LATENCY_TRANSITION 10 |
| 111 | #define PSS_LATENCY_BUSMASTER 10 |
| 112 | |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 113 | /* PCODE MMIO communications live in the MCHBAR. */ |
| 114 | #define BIOS_MAILBOX_INTERFACE 0x5da4 |
| 115 | #define MAILBOX_RUN_BUSY (1 << 31) |
| 116 | #define MAILBOX_BIOS_CMD_READ_PCS 1 |
| 117 | #define MAILBOX_BIOS_CMD_WRITE_PCS 2 |
| 118 | #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 |
| 119 | #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 120 | #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa |
| 121 | #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 122 | /* Errors are returned back in bits 7:0. */ |
| 123 | #define MAILBOX_BIOS_ERROR_NONE 0 |
| 124 | #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 |
| 125 | #define MAILBOX_BIOS_ERROR_TIMEOUT 2 |
| 126 | #define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 |
| 127 | #define MAILBOX_BIOS_ERROR_RESERVED 4 |
| 128 | #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 |
| 129 | #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 |
| 130 | #define MAILBOX_BIOS_ERROR_VR_ERROR 7 |
| 131 | /* Data is passed through bits 31:0 of the data register. */ |
| 132 | #define BIOS_MAILBOX_DATA 0x5da0 |
| 133 | |
Aaron Durbin | 8ce667e | 2013-02-15 21:45:06 -0600 | [diff] [blame] | 134 | /* Region of SMM space is reserved for multipurpose use. It falls below |
| 135 | * the IED region and above the SMM handler. */ |
| 136 | #define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE |
| 137 | #define RESERVED_SMM_OFFSET \ |
| 138 | (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) |
| 139 | |
| 140 | /* Sanity check config options. */ |
| 141 | #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) |
| 142 | # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" |
| 143 | #endif |
| 144 | #if (CONFIG_SMM_TSEG_SIZE < 0x800000) |
| 145 | # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" |
| 146 | #endif |
| 147 | #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) |
| 148 | # error "CONFIG_SMM_TSEG_SIZE is not a power of 2" |
| 149 | #endif |
| 150 | #if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) |
| 151 | # error "CONFIG_IED_REGION_SIZE is not a power of 2" |
| 152 | #endif |
| 153 | |
Stefan Reinauer | 3f5f6d8 | 2013-05-07 20:35:29 +0200 | [diff] [blame] | 154 | #if !defined(__ROMCC__) // FIXME romcc should handle below constructs |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 155 | |
| 156 | #if defined(__PRE_RAM__) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 157 | struct pei_data; |
| 158 | struct rcba_config_instruction; |
| 159 | struct romstage_params { |
| 160 | struct pei_data *pei_data; |
| 161 | const void *gpio_map; |
| 162 | const struct rcba_config_instruction *rcba_config; |
| 163 | unsigned long bist; |
Aaron Durbin | c7633f4 | 2013-06-13 17:29:36 -0700 | [diff] [blame] | 164 | void (*copy_spd)(struct pei_data *); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 165 | }; |
| 166 | void mainboard_romstage_entry(unsigned long bist); |
| 167 | void romstage_common(const struct romstage_params *params); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 168 | /* romstage_main is called from the cache-as-ram assembly file. The return |
| 169 | * value is the stack value to be used for romstage once cache-as-ram is |
| 170 | * torn down. The following values are pushed onto the stack to setup the |
| 171 | * MTRRs: |
| 172 | * +0: Number of MTRRs |
Paul Menzel | 4fe9813 | 2014-01-25 15:55:28 +0100 | [diff] [blame] | 173 | * +4: MTRR base 0 31:0 |
| 174 | * +8: MTRR base 0 63:32 |
| 175 | * +12: MTRR mask 0 31:0 |
| 176 | * +16: MTRR mask 0 63:32 |
| 177 | * +20: MTRR base 1 31:0 |
| 178 | * +24: MTRR base 1 63:32 |
| 179 | * +28: MTRR mask 1 31:0 |
| 180 | * +32: MTRR mask 1 63:32 |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 181 | * ... |
| 182 | */ |
Aaron Durbin | 39ecc65 | 2013-05-02 09:42:13 -0500 | [diff] [blame] | 183 | void * asmlinkage romstage_main(unsigned long bist); |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 184 | /* romstage_after_car() is the C function called after cache-as-ram has |
| 185 | * been torn down. It is responsible for loading the ramstage. */ |
Kyösti Mälkki | b37d01d3 | 2016-07-21 21:08:28 +0300 | [diff] [blame^] | 186 | void asmlinkage romstage_after_car(void); |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 187 | #endif |
| 188 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 189 | #ifdef __SMM__ |
| 190 | /* Lock MSRs */ |
| 191 | void intel_cpu_haswell_finalize_smm(void); |
| 192 | #else |
| 193 | /* Configure power limits for turbo mode */ |
| 194 | void set_power_limits(u8 power_limit_1_time); |
| 195 | int cpu_config_tdp_levels(void); |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 196 | void smm_relocation_handler(int cpu, uintptr_t curr_smbase, |
| 197 | uintptr_t staggered_smbase); |
| 198 | void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 199 | size_t *smm_save_state_size); |
| 200 | void smm_initialize(void); |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 201 | void smm_relocate(void); |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 202 | struct bus; |
| 203 | void bsp_init_and_start_aps(struct bus *cpu_bus); |
Aaron Durbin | 66da043 | 2013-05-28 14:26:29 -0500 | [diff] [blame] | 204 | /* Determine if HyperThreading is disabled. The variable is not valid until |
| 205 | * setup_ap_init() has been called. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 206 | #endif |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 207 | |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 208 | /* CPU identification */ |
| 209 | int haswell_family_model(void); |
| 210 | int haswell_stepping(void); |
| 211 | int haswell_is_ult(void); |
| 212 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 213 | #endif |
| 214 | |
| 215 | #endif |