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review.coreboot.org / coreboot / b2d68976c830c3b4eddf78ea788f02cfa6d25ffc / . / src / vendorcode / amd / agesa / f15 / gcccar.inc
blob: c88709c7c47e6ff16f09a242bbd2a887ccdcd50f [file] [log] [blame]
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]1/*
2 * Copyright (C) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
13 * its contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29/******************************************************************************
30* AMD Generic Encapsulated Software Architecture
31*
32* $Workfile:: GccCar.inc $Revision:: 32932 $
33*
34* Description: GccCar.inc - AGESA cache-as-RAM setup Include File for GCC complier
35*
36******************************************************************************/
37
38.altmacro
39
40BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */
41BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */
42CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
43CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
44CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
45CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
46
47APIC_BASE_ADDRESS = 0x0000001B
48 APIC_BSC = 8 /* Boot Strap Core */
49
50AMD_MTRR_VARIABLE_BASE0 = 0x0200
51AMD_MTRR_VARIABLE_BASE6 = 0x020C
Kostr335450d2012-10-08 22:04:53 +0400[diff] [blame]52AMD_MTRR_VARIABLE_MASK7 = 0x020F
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]53AMD_MTRR_FIX64k_00000 = 0x0250
54AMD_MTRR_FIX16k_80000 = 0x0258
55AMD_MTRR_FIX16k_A0000 = 0x0259
56AMD_MTRR_FIX4k_C0000 = 0x0268
57AMD_MTRR_FIX4k_C8000 = 0x0269
58AMD_MTRR_FIX4k_D0000 = 0x026A
59AMD_MTRR_FIX4k_D8000 = 0x026B
60AMD_MTRR_FIX4k_E0000 = 0x026C
61AMD_MTRR_FIX4k_E8000 = 0x026D
62AMD_MTRR_FIX4k_F0000 = 0x026E
63AMD_MTRR_FIX4k_F8000 = 0x026F
64
Kostr335450d2012-10-08 22:04:53 +0400[diff] [blame]65/* Reproduced from AGESA.h */
66AMD_AP_MTRR_FIX64k_00000 = 0x00000250
67AMD_AP_MTRR_FIX16k_80000 = 0x00000258
68AMD_AP_MTRR_FIX16k_A0000 = 0x00000259
69AMD_AP_MTRR_FIX4k_C0000 = 0x00000268
70AMD_AP_MTRR_FIX4k_C8000 = 0x00000269
71AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A
72AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B
73AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C
74AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D
75AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E
76AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F
77CPU_LIST_TERMINAL = 0xFFFFFFFF
78
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]79AMD_MTRR_DEFTYPE = 0x02FF
80 WB_DRAM_TYPE = 0x1E /* MemType - memory type */
81 MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
82 MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */
83
84HWCR = 0x0C0010015 /* Hardware Configuration */
85 INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */
86
87IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */
88 /* uses 16h - 19h */
89TOP_MEM = 0x0C001001A /* Top of Memory */
90TOP_MEM2 = 0x0C001001D /* Top of Memory2 */
91
92LS_CFG = 0x0C0011020 /* Load-Store Configuration */
93 DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */
94 DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */
95
96IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */
97 IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */
98 DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */
99 DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */
100
101DC_CFG = 0x0C0011022 /* Data Cache Configuration */
102 DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */
103 DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */
104 DIS_HW_PF = 13 /* Hardware prefetches bit */
105
106DE_CFG = 0x0C0011029 /* Decode Configuration */
107 CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */
108
109BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */
110CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */
111 F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */
112 IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */
113
114CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */
115 COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
116
117
Konstantin Aladyshevc2f2bd02013-03-06 22:13:42 +0400[diff] [blame]118CR0_PE = 0 # Protection Enable
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]119CR0_NW = 29 # Not Write-through
120CR0_CD = 30 # Cache Disable
121CR0_PG = 31 # Paging Enable
122
123/* CPUID Functions */
124
125CPUID_MODEL = 1
126AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */
127AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */
128
129NB_CFG = 0x0C001001F /* Northbridge Configuration Register */
130 INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */
131
132MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */
133 CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */
134 SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */
135 MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */
136 MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */
137 MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */
138 MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */
139
140PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */
141 PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */
142 PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */
143 CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */
144 CONFIG_EVENT_H = 4 /* Increment count by number of event */
145 /* occured in clock cycle */
146 EVENT_ENABLE = 22 /* Enable the event */
147PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */
148
149# Local use flags, in upper most byte if ESI
150FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized
151FLAG_STACK_REENTRY = 25 # Signals that the environment has made a re-entry (2nd) call to set up the stack
152FLAG_IS_PRIMARY = 26 # Signals that this core is the primary within the comoute unit
153
154CR0_MASK = ((1 << CR0_CD) | (1 << CR0_NW))
155MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
156
157/****************************************************************************
158 *
159 * CPU MACROS - PUBLIC
160 *
161 ****************************************************************************/
162.macro _WRMSR
163 .byte 0x0f, 0x30
164.endm
165
166.macro _RDMSR
167 .byte 0x0F, 0x32
168.endm
169
170.macro AMD_CPUID arg0
171 .ifb \arg0
172 mov $0x1, %eax
173 .byte 0x0F, 0x0A2 /* Execute instruction */
174 bswap %eax
175 xchg %ah, %al /* Ext model in al now */
176 rol $0x08, %eax /* Ext model in ah, model in al */
177 and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */
178 .else
179 mov \arg0, %eax
180 .byte 0x0F, 0x0A2
181 .endif
182.endm
183
184/****************************************************************************
185*
186* AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
187*
188* Set any family specific controls needed to enable the use of
189* cache as general storage before main memory is available.
190*
191* Inputs:
192* none
193* Outputs:
194* none
195 ****************************************************************************/
196.macro AMD_ENABLE_STACK_FAMILY_HOOK
197
198 AMD_ENABLE_STACK_FAMILY_HOOK_F10
199 AMD_ENABLE_STACK_FAMILY_HOOK_F12
200 AMD_ENABLE_STACK_FAMILY_HOOK_F14
201 AMD_ENABLE_STACK_FAMILY_HOOK_F15
202.endm
203
204/****************************************************************************
205*
206* AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
207*
208* Return any family specific controls to their 'standard'
209* settings for using cache with main memory.
210*
211* Inputs:
212* none
213* Outputs:
214* none
215 ****************************************************************************/
216.macro AMD_DISABLE_STACK_FAMILY_HOOK
217
218 AMD_DISABLE_STACK_FAMILY_HOOK_F10
219 AMD_DISABLE_STACK_FAMILY_HOOK_F12
220 AMD_DISABLE_STACK_FAMILY_HOOK_F14
221 AMD_DISABLE_STACK_FAMILY_HOOK_F15
222
223.endm
224
225/****************************************************************************
226*
227* GET_NODE_ID_CORE_ID Macro - Stackless
228*
229* Read family specific values to determine the node and core
230* numbers for the core executing this code.
231*
232* Inputs:
233* none
234* Outputs:
235* SI[7:0] = Core# (0..N, relative to node)
236* SI[15:8]= Node# (0..N)
237* SI[23:16]= reserved
238* SI[24]= flag: 1=Family Unrecognized
239* SI[25]= flag: 1=Interface re-entry call
240* SI[26]= flag: 1=Core is primary of compute unit
241* SI[31:27]= reserved, =0
242****************************************************************************/
243.macro GET_NODE_ID_CORE_ID
244 LOCAL node_core_exit
245
246 mov $-1, %si
247 GET_NODE_ID_CORE_ID_F10
248 GET_NODE_ID_CORE_ID_F12
249 GET_NODE_ID_CORE_ID_F14
250 GET_NODE_ID_CORE_ID_F15
251 /*
252 * Check for unrecognized Family
253 */
254 cmp $-1, %si # Has family (node/core) already been discovered?
255 jnz node_core_exit # Br if yes
256
257 mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
258
259 mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
260 _RDMSR
261 bt $APIC_BSC, %eax # Is this the BSC?
262 jc node_core_exit # Br if yes
263 hlt # Kill APs
264node_core_exit:
265
266.endm
267
268/****************************************************************************
269## Family 10h MACROS
270##***************************************************************************
271#---------------------------------------------------
272#
273# AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
274#
275# Set any family specific controls needed to enable the use of
276# cache as general storage before main memory is available.
277#
278# Inputs:
279# ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
280# Outputs:
281# none
282#
283# Family 10h requirements (BKDG section 2.3.3):
284# * Paging disabled
285# * MSRC001_0015[INVDWBINVD]=0
286# * MSRC001_1021[DIS_IND]=1
287# * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
288# * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
289# * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1
290# * MSRC001_1022[DIS_HW_PF]=1
291# * MSRC001_102A[IcDisSpecTlbWr]=1
292# * MSRC001_102A[ClLinesToNbDis]=1
293# * No INVD or WBINVD, no exceptions, page faults or interrupts
294****************************************************************************/
295.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
296 LOCAL fam10_enable_stack_hook_exit
297
298 AMD_CPUID $CPUID_MODEL
299 shr $20, %eax # AL = cpu extended family
300 cmp $0x01, %al # Is this family 10h?
301 jnz fam10_enable_stack_hook_exit # Br if no
302
303 mov $DC_CFG, %ecx # MSR:C001_1022
304 _RDMSR
305 bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DTLB reloads bit
306 bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Turn on Disable the self modifying code check buffer bit
307 bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit
308 _WRMSR
309
310 dec %cx # MSR:C001_1021
311 _RDMSR
312 bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative TLB reloads bit
313 bts $DIS_IND, %eax # Turn on Disable indirect branch predictor
314 _WRMSR
315
316 mov $BU_CFG2, %ecx # MSR C001_102A
317 _RDMSR
318 bts $F10_CL_LINES_TO_NB_DIS, %eax # Allow BIOS ROM to be cached in the IC
319 bts $(IC_DIS_SPEC_TLB_WR-32), %edx #Disable speculative writes to the ITLB
320 _WRMSR
321
322 mov $HWCR, %ecx # MSR C001_0015
323 _RDMSR
324 bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set
325 jc fam10_skipClearingBit4
326 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
327 _WRMSR
328
329fam10_skipClearingBit4:
330 mov %esi, %eax # load core#
331 or %al, %al # If (BSP)
332 jne fam10_enable_stack_hook_exit
333 mov $PERF_COUNTER3, %ecx # Select performance counter three
334 # to count number of CAR evictions
335 xor %eax, %eax # Initialize the lower part of the counter to zero
336 xor %edx, %edx # Initializa the upper part of the counter to zero
337 _WRMSR # Save it
338 mov $PERF_CONTROL3, %ecx # Select the event control three
339 _RDMSR # Get the current setting
340 and $PERF_CONTROL3_RESERVE_L, %eax # Preserve the reserved bits
341 or $CONFIG_EVENT_L, %eax # Set the lower part of event register to
342 # select CAR Corruption occurred by any cores
343 and $PERF_CONTROL3_RESERVE_H, %dx # Preserve the reserved bits
344 or $CONFIG_EVENT_H, %dx # Set the upper part of event register
345 _WRMSR # Save it
346 bts $EVENT_ENABLE, %eax # Enable it
347 _WRMSR # Save it
348
349fam10_enable_stack_hook_exit:
350.endm
351
352/****************************************************************************
353*
354* AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
355*
356* Return any family specific controls to their 'standard'
357* settings for using cache with main memory.
358*
359* Inputs:
360* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
361* Outputs:
362* none
363*
364* Family 10h requirements:
365* * INVD or WBINVD
366* * MSRC001_0015[INVD_WBINVD]=1
367* * MSRC001_1021[DIS_IND]=0
368* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
369* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
370* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0
371* * MSRC001_1022[DIS_HW_PF]=0
372* * MSRC001_102A[IcDisSpecTlbWr]=0
373* * MSRC001_102A[ClLinesToNbDis]=0
374*****************************************************************************/
375
376.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10
377 LOCAL fam10_disable_stack_hook_exit
378
379 AMD_CPUID $CPUID_MODEL
380 shr $20, %eax # AL = cpu extended family
381 cmp $0x01, %al # Is this family 10h?
382 jnz fam10_disable_stack_hook_exit # Br if no
383
384 mov $DC_CFG, %ecx # MSR:C001_1022
385 _RDMSR
386 btr $DC_DIS_SPEC_TLB_RLD, %eax # Enable speculative TLB reloads
387 btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Allow self modifying code check buffer
388 btr $DIS_HW_PF, %eax # Allow hardware prefetches
389 _WRMSR
390
391 dec %cx # MSR:C001_1021
392 _RDMSR
393 btr $DIS_IND, %eax # Turn on indirect branch predictor
394 btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
395 _WRMSR
396
397 mov $BU_CFG2, %ecx # MSR:C001_102A
398 _RDMSR
399/*
400 * BTS error if SBIOS `allows WP code to be cached', but copying
401 * ramstage/payloads from ROM to RAM will be very slow if disable it here.
402 *
403 * TODO: disable `allows WP code to be cached' after the ROM to RAM copying.
404 */
405// btr $F10_CL_LINES_TO_NB_DIS, %eax # Return L3 to normal mode
406 btr $(IC_DIS_SPEC_TLB_WR-32), %edx #Re-enable speculative writes to the ITLB
407 _WRMSR
408
409 #--------------------------------------------------------------------------
410 # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
411 #--------------------------------------------------------------------------
412
413 mov $HWCR, %ecx # MSR:0000_0015
414 _RDMSR
415 mov %ax, %bx # Save INVD -> WBINVD bit
416 btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion for the invd instruction.
417 _WRMSR
418 wbinvd # Clear the cache tag RAMs
419 mov %bx, %ax # Restore INVD -> WBINVD bit
420 _WRMSR
421
422 #--------------------------------------------------------------------------
423 # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
424 #--------------------------------------------------------------------------
425
426 mov $PERF_CONTROL3, %ecx # Select the event control three
427 _RDMSR # Retrieve the current value
428 btc $EVENT_ENABLE, %eax # Is event enable, complement it as well
429 jnc fam10_disable_stack_hook_exit # No
430 cmp $CONFIG_EVENT_L, %ax # Is the lower part of event set to capture the CAR Corruption
431 jne fam10_disable_stack_hook_exit # No
432 cmp $CONFIG_EVENT_H, %dl # Is the upper part of event set to capture the CAR Corruption
433 jne fam10_disable_stack_hook_exit # No
434 _WRMSR # Disable the event
435
436fam10_disable_stack_hook_exit:
437.endm
438
439/****************************************************************************
440*
441* GET_NODE_ID_CORE_ID_F10 Macro - Stackless
442*
443* Read family specific values to determine the node and core
444* numbers for the core executing this code.
445*
446* Inputs:
447* none
448* Outputs:
449* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
450*****************************************************************************/
451.macro GET_NODE_ID_CORE_ID_F10
452
453 LOCAL node_core_f10_exit
454 LOCAL node_core_f10_AP
455
456 cmp $-1, %si # Has node/core already been discovered?
457 jnz node_core_f10_exit # Br if yes
458
459 AMD_CPUID $CPUID_MODEL
460 shr $20, %eax # AL = cpu extended family
461 cmp $0x01, %al # Is this family 10h?
462 jnz node_core_f10_exit # Br if no
463
464 xor %esi, %esi # Assume BSC, clear flags
465 mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
466 _RDMSR
467 bt $APIC_BSC, %eax # Is this the BSC?
468 jnc node_core_f10_AP # Br if no
469
470 # This is the BSP.
471 # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
472 mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register
473 mov $0x0CF8, %dx
474 out %eax, %dx
475 add $4, %dx
476 in %dx, %eax
477 btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0
478 out %eax, %dx
479 jmp 1f #
480
481node_core_f10_AP:
482 #
483 # This is an AP. Routing tables have been enabled by the HT Init process.
484 # Also, the MailBox register was set by the BSP during early init
485 # The Mailbox register content is formatted as follows:
486 # UINT32 Node:4# // The node id of Core's node.
487 # UINT32 Socket:4# // The socket of this Core's node.
488 # UINT32 Module:2# // The internal module number for Core's node.
489 # UINT32 ModuleType:2# // Single Module = 0, Multi-module = 1.
490 # UINT32 :20# // Reserved
491 #
492 mov $0x0C0000408, %ecx # Read the family 10h mailbox
493 _RDMSR # MC4_MISC1[63:32]
494 mov %dx, %si # SI = raw mailbox contents (will extract node# from this)
495 shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId]
496 mov %bx, %di # DI = Initial APIC ID (will extract core# from this)
497
498 AMD_CPUID $AMD_CPUID_APIC #
499 shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core#
500 inc %cl # CL = Number of enabled cores in the socket
501 mov %cx, %bx
502
503 mov $NB_CFG, %ecx # MSR:C001_001F
504 _RDMSR # EDX has InitApicIdCpuIdLo bit
505
506 mov %bh, %cl # CL = APIC ID size
507 mov $1, %al # Convert APIC ID size to an AND mask
508 shl %cl, %al # AL = 2^APIC ID size
509 dec %al # AL = mask for relative core number
510 xor %ah, %ah # AX = mask for relative core number
511 bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?
512 #.if (!carry?) # Br if yes
513 jc 0f
514 mov $8, %ch # Calculate core number shift count
515 sub %cl, %ch # CH = core shift count
516 mov %ch, %cl
517 shr %cl, %di # Right justify core number
518 #.endif
519 0:
520 and %ax, %di # DI = socket-relative core number
521
522 mov %si, %cx # CX = raw mailbox value
523 shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
524 and $3, %cl # Isolate ModuleType
525 xor %bh, %bh # BX = Number of enabled cores in the socket
526 shr %cl, %bx # BX = Number of enabled cores per node
527 xor %dx, %dx # Clear upper word for div
528 mov %di, %ax # AX = socket-relative core number
529 div %bx # DX = node-relative core number
530 movzx %si, %eax # prepare return value, [23:16]=shared Core# (=0, not shared)
531 and $0x000F, %ax # AX = node number
532 shl $8, %ax # [15:8]=node#
533 mov %dl, %al # [7:0]=core# (relative to node)
534 mov %eax, %esi # ESI = return value
5351:
536 bts $FLAG_IS_PRIMARY, %esi # all Family 10h cores are primary
537node_core_f10_exit:
538.endm
539
540
541/*****************************************************************************
542** Family 12h MACROS
543*****************************************************************************/
544/*****************************************************************************
545*
546* AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless
547*
548* Set any family specific controls needed to enable the use of
549* cache as general storage before main memory is available.
550*
551* Inputs:
552* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
553* Outputs:
554* none
555*
556* Family 12h requirements (BKDG section 2.3.3):
557* The following requirements must be satisfied prior to using the cache as general storage:
558* * Paging must be disabled.
559* * MSRC001_0015[INVD_WBINVD]=0
560* * MSRC001_1020[DIS_SS]=1
561* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
562* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
563* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1
564* * MSRC001_1022[DIS_HW_PF]=1
565* * MSRC001_1029[ClflushSerialize]=1
566* * No INVD or WBINVD, no exceptions, page faults or interrupts
567*****************************************************************************/
568.macro AMD_ENABLE_STACK_FAMILY_HOOK_F12
569 LOCAL fam12_enable_stack_hook_exit
570
571 AMD_CPUID $CPUID_MODEL
572 shr $20, %eax # AL = cpu extended family
573 cmp $0x03, %al # Is this family 12h?
574 jnz fam12_enable_stack_hook_exit # Br if no
575
576 mov $DC_CFG, %ecx # MSR:C001_1022
577 _RDMSR
578 bts $DC_DIS_SPEC_TLB_RLD, %eax # Disable speculative DC-TLB reloads
579 bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Disable self modifying code check buffer
580 bts $DIS_HW_PF, %eax # Disable hardware prefetches
581 _WRMSR
582
583 dec %cx #IC_CFG # MSR:C001_1021
584 _RDMSR
585 bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative IC-TLB reloads
586 _WRMSR
587
588 dec %cx #LS_CFG # MSR:C001_1020
589 _RDMSR
590 bts $DIS_SS, %eax # Disabled Streaming store functionality
591 _WRMSR
592
593 mov $HWCR, %ecx # MSR C001_0015
594 _RDMSR
595 bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set
596 jc fam12_skipClearingBit4
597 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
598 _WRMSR
599
600fam12_skipClearingBit4:
601 mov $DE_CFG, %ecx # MSR:C001_1029
602 _RDMSR
603 bts $CL_FLUSH_SERIALIZE, %eax # Serialize all CL Flush actions
604 _WRMSR
605
606fam12_enable_stack_hook_exit:
607.endm
608
609/*****************************************************************************
610*
611* AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless
612*
613* Return any family specific controls to their 'standard'
614* settings for using cache with main memory.
615*
616* Inputs:
617* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
618* Outputs:
619* none
620*
621* Family 12h requirements:
622* * INVD or WBINVD
623* * MSRC001_0015[INVD_WBINVD]=1
624* * MSRC001_1020[DIS_SS]=0
625* * MSRC001_1021[IC_DIS_SPEC_TLB_RLD]=0
626* * MSRC001_1022[DC_DIS_SPEC_TLB_RLD]=0
627* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0
628* * MSRC001_1022[DIS_HW_PF]=0
629* * MSRC001_1029[ClflushSerialize]=0
630*****************************************************************************/
631.macro AMD_DISABLE_STACK_FAMILY_HOOK_F12
632 LOCAL fam12_disable_stack_hook_exit
633
634 AMD_CPUID $CPUID_MODEL
635 shr $20, %eax # AL = cpu extended family
636 cmp $0x03, %al # Is this family 12h?
637 jnz fam12_disable_stack_hook_exit # Br if no
638
639 mov $DC_CFG, %ecx # MSR:C001_1022
640 _RDMSR
641 btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads
642 btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Enable self modifying code check buffer
643 btr $DIS_HW_PF, %eax # Enable Hardware prefetches
644 _WRMSR
645
646 dec %cx #IC_CFG # MSR:C001_1021
647 _RDMSR
648 btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative IC-TLB reloads
649 _WRMSR
650
651 dec %cx #LS_CFG # MSR:C001_1020
652 _RDMSR
653 btr $DIS_SS, %eax # Turn on Streaming store functionality
654 _WRMSR
655
656 mov $DE_CFG, %ecx # MSR:C001_1029
657 _RDMSR
658 btr $CL_FLUSH_SERIALIZE, %eax
659 _WRMSR
660
661 #--------------------------------------------------------------------------
662 # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
663 #--------------------------------------------------------------------------
664
665 mov $HWCR, %ecx # MSR:0000_0015h
666 _RDMSR
667 mov %ax, %bx # Save INVD -> WBINVD bit
668 btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
669 _WRMSR
670 invd # Clear the cache tag RAMs
671 mov %bx, %ax # Restore INVD -> WBINVD bit
672 _WRMSR
673
674 #--------------------------------------------------------------------------
675 # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
676 #--------------------------------------------------------------------------
677
678fam12_disable_stack_hook_exit:
679.endm
680
681/*****************************************************************************
682*
683* GET_NODE_ID_CORE_ID_F12 Macro - Stackless
684*
685* Read family specific values to determine the node and core
686* numbers for the core executing this code.
687*
688* Inputs:
689* none
690* Outputs:
691* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
692*****************************************************************************/
693.macro GET_NODE_ID_CORE_ID_F12
694
695 LOCAL node_core_f12_exit
696
697 cmp $-1, %si # Has node/core already been discovered?
698 jnz node_core_f12_exit # Br if yes
699
700 AMD_CPUID $CPUID_MODEL
701 shr $20, %eax # AL = cpu extended family
702 cmp $0x03, %al # Is this family 12h?
703 jnz node_core_f12_exit # Br if no
704
705 shr $24, %ebx # CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID
706 bts $FLAG_IS_PRIMARY, %ebx # all family 12h cores are primary
707 mov %ebx, %esi # ESI = Node#=0, core number
708node_core_f12_exit:
709.endm
710
711/*****************************************************************************
712** Family 14h MACROS
713*****************************************************************************/
714/*****************************************************************************
715*
716* AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless
717*
718* Set any family specific controls needed to enable the use of
719* cache as general storage before main memory is available.
720*
721* Inputs:
722* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
723* Outputs:
724* none
725*
726* Family 14h requirements (BKDG section 2.3.3):
727* * Paging must be disabled.
728* * MSRC001_0015[INVD_WBINVD]=0.
729* * MSRC001_1020[DisStreamSt]=1.
730* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
731* * MSRC001_1022[DIS_HW_PF]=1.
732* * No INVD or WBINVD, no exceptions, page faults or interrupts
733*****************************************************************************/
734.macro AMD_ENABLE_STACK_FAMILY_HOOK_F14
735 LOCAL fam14_enable_stack_hook_exit
736
737 AMD_CPUID $CPUID_MODEL
738 shr $20, %eax # AL = cpu extended family
739 cmp $0x05, %al # Is this family 14h?
740 jnz fam14_enable_stack_hook_exit # Br if no
741
742 mov $DC_CFG, %ecx # MSR:C001_1022
743 _RDMSR
744 bts $DIS_HW_PF, %eax # Disable hardware prefetches
745 _WRMSR
746
747 dec %cx #IC_CFG # MSR:C001_1021
748 _RDMSR
749 bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative TLB reloads
750 _WRMSR
751
752 dec %cx #LS_CFG # MSR:C001_1020
753 _RDMSR
754 bts $DIS_STREAM_ST, %eax # Disabled Streaming store functionality
755 _WRMSR
756
757 mov $HWCR, %ecx # MSR C001_0015
758 _RDMSR
759 bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set
760 jc fam14_skipClearingBit4
761 btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
762 _WRMSR
763fam14_skipClearingBit4: # Keeping this label
764
765fam14_enable_stack_hook_exit:
766.endm
767
768/*****************************************************************************
769*
770* AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless
771*
772* Return any family specific controls to their 'standard'
773* settings for using cache with main memory.
774*
775* Inputs:
776* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
777* Outputs:
778* none
779*
780* Family 14h requirements:
781* * INVD or WBINVD
782* * MSRC001_0015[INVD_WBINVD]=1.
783* * MSRC001_1020[DisStreamSt]=0.
784* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0.
785* * MSRC001_1022[DIS_HW_PF]=0.
786*****************************************************************************/
787.macro AMD_DISABLE_STACK_FAMILY_HOOK_F14
788 LOCAL fam14_disable_stack_hook_exit
789
790 AMD_CPUID $CPUID_MODEL
791 shr $20, %eax # AL = cpu extended family
792 cmp $0x05, %al # Is this family 14h?
793 jnz fam14_disable_stack_hook_exit # Br if no
794
795 mov $LS_CFG, %ecx # MSR:C001_1020
796 _RDMSR
797 btr $DIS_STREAM_ST, %eax # Turn on Streaming store functionality
798 _WRMSR
799
800 inc %cx #IC_CFG # MSR:C001_1021
801 _RDMSR
802 btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads
803 _WRMSR
804
805 inc %cx #DC_CFG # MSR:C001_1022
806 _RDMSR
807 btr $DIS_HW_PF, %eax # Turn on hardware prefetches
808 _WRMSR
809
810 #--------------------------------------------------------------------------
811 # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
812 #--------------------------------------------------------------------------
813
814 mov $HWCR, %ecx # MSR:C001_0015h
815 _RDMSR
816 btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
817 _WRMSR
818 invd # Clear the cache tag RAMs
819 bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
820 _WRMSR
821
822 #--------------------------------------------------------------------------
823 # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
824 #--------------------------------------------------------------------------
825
826fam14_disable_stack_hook_exit:
827.endm
828
829/*****************************************************************************
830*
831* GET_NODE_ID_CORE_ID_F14 Macro - Stackless
832*
833* Read family specific values to determine the node and core
834* numbers for the core executing this code.
835*
836* Inputs:
837* none
838* Outputs:
839* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
840*****************************************************************************/
841.macro GET_NODE_ID_CORE_ID_F14
842
843 LOCAL node_core_f14_exit
844
Edward O'Callaghan9cd96b42014-02-21 12:43:07 +1100[diff] [blame]845 cmp $-1, %si # Has node/core already been discovered?
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]846 jnz node_core_f14_exit # Br if yes
847
848 AMD_CPUID $CPUID_MODEL
849 shr $20, %eax # AL = cpu extended family
850 cmp $0x05, %al # Is this family 14h?
851 jnz node_core_f14_exit # Br if no
852
853 xor %esi, %esi # Node must be 0
854 bts $FLAG_IS_PRIMARY, %esi # all family 14h cores are primary
855 mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
856 _RDMSR
857 bt $APIC_BSC, %eax # Is this the BSC?
858 jc node_core_f14_exit # Br if yes
859 inc %si # Set core to 1
860node_core_f14_exit:
861.endm
862
863
864
865/*****************************************************************************
866** Family 15h MACROS
867*****************************************************************************/
868/*****************************************************************************
869*
870* AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
871*
872* Set any family specific controls needed to enable the use of
873* cache as general storage before main memory is available.
874*
875* Inputs:
876* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
877* Outputs:
878* none
879*
880* Family 15h requirements (BKDG #42301 section 2.3.3):
881* * Paging must be disabled.
882* * MSRC001_0015[INVD_WBINVD]=0
883* * MSRC001_1020[DisSS]=1
884* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
885* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
886* * MSRC001_1022[DisHwPf]=1
887* * No INVD or WBINVD, no exceptions, page faults or interrupts
888*****************************************************************************/
889.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15
890 LOCAL fam15_enable_stack_hook_exit
891
892 AMD_CPUID $CPUID_MODEL
893 shr $20, %eax # AL = cpu extended family
894 cmp $0x06, %al # Is this family 15h?
895 jnz fam15_enable_stack_hook_exit # Br if no
896
897 bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set
898 jc fam15_skipClearingBit4
899 mov $HWCR, %ecx # MSR C001_0015
900 _RDMSR
901 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
902 _WRMSR
903
904fam15_skipClearingBit4:
905 mov $LS_CFG, %ecx # MSR:C001_1020
906 _RDMSR
907 bts $DIS_SS, %eax # Turn on Streaming store functionality disabled bit
908 _WRMSR
909
910 inc %ecx #IC_CFG # MSR:C001_1021
911 _RDMSR
912 bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative IC-TLB reloads bit
913 _WRMSR
914
915 inc %ecx #DC_CFG # MSR:C001_1022
916 _RDMSR
917 bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DC-TLB reloads bit
918 bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit
919 _WRMSR
920
921 mov $CU_CFG3, %ecx # MSR:C001_102B
922 _RDMSR
923 btr $(COMBINE_CR0_CD - 32), %edx # Clear CombineCr0Cd bit
924 _WRMSR
925
926fam15_enable_stack_hook_exit:
927.endm
928
929
930/*****************************************************************************
931*
932* AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
933*
934* Return any family specific controls to their 'standard'
935* settings for using cache with main memory.
936*
937* Inputs:
938* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
939* Outputs:
940* none
941*
942* Family 15h requirements:
943* * INVD or WBINVD
944* * MSRC001_0015[INVD_WBINVD]=1
945* * MSRC001_1020[DisSS]=0
946* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
947* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
948* * MSRC001_1022[DIS_HW_PF]=0
949*****************************************************************************/
950.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15
951 LOCAL fam15_disable_stack_hook_exit
952
953 AMD_CPUID $CPUID_MODEL
954 mov %eax, %ebx # Save revision info to EBX
955 shr $20, %eax # AL = cpu extended family
956 cmp $0x06, %al # Is this family 15h?
957 jnz fam15_disable_stack_hook_exit # Br if no
958
959 mov $LS_CFG, %ecx # MSR:C001_1020
960 #.if (ebx != 00600F00h) ; Is this rev A0?
961 cmp $0x00600F00, %ebx
962 jz 0f
963 _RDMSR
964 btr $DIS_SS, %eax # Turn on Streaming store functionality
965 _WRMSR
966 #.endif
967 0: # End workaround for errata 495 and 496
968
969 inc %ecx #IC_CFG # MSR:C001_1021
970 _RDMSR
971 btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
972 _WRMSR
973
974 inc %ecx #DC_CFG # MSR:C001_1022
975 _RDMSR
976 btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
977 #.if (ebx != 00600F00h) # Is this rev A0?
978 cmp $0x00600F00, %ebx
979 jz 0f
980 btr $DIS_HW_PF, %eax # Turn on hardware prefetches
981 #.endif # End workaround for erratum 498
982 0:
983 _WRMSR
984 #--------------------------------------------------------------------------
985 # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
986 #--------------------------------------------------------------------------
987
988 bt $FLAG_IS_PRIMARY, %esi
989 #.if (carry?) # Only clear cache from primary core
990 jnc 0f
991 mov $HWCR, %ecx # MSR:C001_0015h
992 _RDMSR
993 btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
994 _WRMSR
995 wbinvd # Clear the cache tag RAMs
996 bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
997 _WRMSR
998 #.endif # end
999 0:
1000
1001 #--------------------------------------------------------------------------
1002 # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
1003 #--------------------------------------------------------------------------
1004
1005 mov $CU_CFG3, %ecx # MSR:C001_102B
1006 _RDMSR
Konstantin Aladyshev7fcbbb02013-03-06 19:58:38 +0400[diff] [blame]1007 bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit
Kerry Shehe8689ed2012-01-20 13:57:48 +0800[diff] [blame]1008 _WRMSR
1009
1010fam15_disable_stack_hook_exit:
1011.endm
1012
1013
1014/*****************************************************************************
1015*
1016* GET_NODE_ID_CORE_ID_F15 Macro - Stackless
1017*
1018* Read family specific values to determine the node and core
1019* numbers for the core executing this code.
1020*
1021* Inputs:
1022* none
1023* Outputs:
1024* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
1025*****************************************************************************/
1026.macro GET_NODE_ID_CORE_ID_F15
1027
1028 LOCAL node_core_f15_exit
1029 LOCAL node_core_f15_AP
1030 LOCAL node_core_f15_shared
1031
1032 cmp $-1, %si # Has node/core already been discovered?
1033 jnz node_core_f15_exit # Br if yes
1034
1035 AMD_CPUID $CPUID_MODEL
1036 shr $20, %eax # AL = cpu extended family
1037 cmp $06, %al # Is this family 15h?
1038 jnz node_core_f15_exit # Br if no
1039
1040 xor %esi, %esi # Assume BSC, clear local flags
1041 mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
1042 _RDMSR
1043 bt $APIC_BSC, %eax # Is this the BSC?
1044 jnc node_core_f15_AP # Br if no
1045
1046 # This is the BSP.
1047 # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
1048 mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register
1049 mov $0x0CF8, %dx
1050 out %eax, %dx
1051 add $4, %dx
1052 in %dx, %eax
1053 btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0
1054 out %eax, %dx
1055 jmp node_core_f15_shared #
1056
1057node_core_f15_AP:
1058 #
1059 # This is an AP. Routing tables have been enabled by the HT Init process.
1060 # Also, the MailBox register was set by the BSP during early init
1061 # The Mailbox register content is formatted as follows:
1062 # UINT32 Node:4; // The node id of Core's node.
1063 # UINT32 Socket:4; // The socket of this Core's node.
1064 # UINT32 Module:2; // The internal module number for Core's node.
1065 # UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1.
1066 # UINT32 :20; // Reserved
1067 #
1068 mov $0x0C0000408, %ecx # Read the family 15h mailbox
1069 _RDMSR # MC4_MISC1[63:32]
1070 mov %dx, %si # SI = raw mailbox contents (will extract node# from this)
1071 shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId]
1072 mov %bx, %di # DI = Initial APIC ID (will extract core# from this)
1073
1074 AMD_CPUID $AMD_CPUID_APIC #
1075 shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core#
1076 inc %cl # CL = Number of enabled cores in the socket
1077 mov %cx, %bx
1078
1079 mov $NB_CFG, %ecx
1080 _RDMSR # EDX has InitApicIdCpuIdLo bit
1081
1082 mov %bh, %cl # CL = APIC ID size
1083 mov $1, %al # Convert APIC ID size to an AND mask
1084 shl %cl, %al # AL = 2^APIC ID size
1085 dec %al # AL = mask for relative core number
1086 xor %ah, %ah # AX = mask for relative core number
1087 bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?
1088 #.if (!carry?) # Br if yes
1089 jc 0f
1090 mov $8, %ch # Calculate core number shift count
1091 sub %cl, %ch # CH = core shift count
1092 mov %ch, %cl
1093 shr %cl, %di # Right justify core number
1094 #.endif
1095 0:
1096 and %ax, %di # DI = socket-relative core number
1097
1098 mov %si, %cx # CX = raw mailbox value
1099 shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
1100 and $3, %cl # Isolate ModuleType
1101 xor %bh, %bh # BX = Number of enabled cores in the socket
1102 shr %cl, %bx # BX = Number of enabled cores per node
1103 xor %dx, %dx # Clear upper word for div
1104 mov %di, %ax # AX = socket-relative core number
1105 div %bx # DX = node-relative core number
1106 movzx %si, %eax # Prepare return value
1107 and $0x000F, %ax # AX = node number
1108 shl $8,%ax # [15:8]=node#
1109 mov %dl, %al # [7:0]=core# (relative to node)
1110 mov %eax, %esi # ESI = node-relative core number
1111
1112 #
1113 # determine if this core shares MTRRs
1114 #
1115node_core_f15_shared:
1116 mov $0x8000C580, %eax # Compute Unit Status
1117 mov %si, %bx
1118 shl $3, %bh # Move node# to PCI Dev# field
1119 add %bh, %ah # Adjust for node number
1120 mov $0x0CF8, %dx
1121 out %eax, %dx
1122 add $4, %dx
1123 in %dx, %eax # [3:0]=Enabled# [19:16]=DualCore
1124
1125 # BL is MyCore#
1126 mov $0x06, %cx # Use CH as 'first of pair' core#
1127 #.while (cl > 0)
1128 jmp 0f
1129 8:
1130 bt $0, %eax # Is pair enabled?
1131 #.if (carry?) #
1132 jnc 1f
1133 mov $0x01, %bh # flag core as primary
1134 bt $16, %eax # Is there a 2nd in the pair?
1135 #.if (carry?) #
1136 jnc 4f
1137 #.break .if (ch == bl) # Does 1st match MyCore#?
1138 cmp %bl, %ch
1139 je 9f
1140 inc %ch
1141 xor %bh, %bh # flag core as NOT primary
1142 #.break .if (ch == bl) # Does 2nd match MyCore#?
1143 cmp %bl, %ch
1144 je 9f
1145 jmp 2f
1146 #.else # No 2nd core
1147 4:
1148 #.break .if (ch == bl) # Does 1st match MyCore#?
1149 cmp %bl, %ch
1150 je 9f
1151 #.endif
1152 2:
1153 inc %ch
1154 #.endif
1155 1:
1156 shr $1, %eax
1157 dec %cl
1158 #.endw
1159 0:
1160 #.if (cl == 0)
1161 cmp $0x0, %cl
1162 ja 8b
1163 9:
1164 or %cl, %cl
1165 jne 1f
1166 #Error - core# didn't match Compute Unit Status content
1167 bts $FLAG_UNKNOWN_FAMILY, %esi
1168 bts $FLAG_IS_PRIMARY, %esi # Set Is_Primary for unknowns
1169 #.endif
1170 1:
1171 #.if (bh != 0) # Check state of primary for the matched core
1172 or %bh, %bh
1173 je 2f
1174 bts $FLAG_IS_PRIMARY, %esi # Set shared flag into return value
1175 #.endif
1176 2:
1177
1178node_core_f15_exit:
1179
1180.endm
1181
1182/*****************************************************************************
1183* AMD_ENABLE_STACK: Setup a stack
1184*
1185* In:
1186* EBX = Return address (preserved)
1187*
1188* Out:
1189* SS:ESP - Our new private stack location
1190*
1191* EAX = AGESA_STATUS
1192*
1193* ECX = Stack size in bytes
1194*
1195* Requirements:
1196* * This routine presently is limited to a max of 64 processor cores
1197* Preserved:
1198* ebx ebp
1199* Destroyed:
1200* eax, ecx, edx, edi, esi, ds, es, ss, esp
1201* mmx0, mmx1
1202*
1203* Description:
1204* Fixed MTRR address allocation to cores:
1205* The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
1206* There is a max of 1 BSP, 7 core0s and 56 other cores.
1207* Although each core has it's own cache storage, they share the address space. Each core must
1208* be assigned a private and unique address space for its stack. To support legacy systems,
1209* the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
1210* for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
1211*
1212* 80000h 40000h 00000h
1213* +----------+----------+----------+----------+----------+----------+----------+----------+
1214* 64K | | | | | | | | | 64K ea
1215* ea +----------+----------+----------+----------+----------+----------+----------+----------+
1216* | MTRR 0000_0250 MTRRfix64K_00000 |
1217* +----------+----------+----------+----------+----------+----------+----------+----------+
1218* | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
1219* |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
1220* +----------+----------+----------+----------+----------+----------+----------+----------+
1221*
1222* C0000h B0000h A0000h 90000h 80000h
1223* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
1224*16K | | | | | | | | | | | | | | | | |
1225* ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
1226* | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
1227* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
1228* | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
1229* | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
1230* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
1231*
1232* E0000h D0000h C0000h
1233* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1234* 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
1235* ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1236* | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
1237* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1238* | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
1239* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1240*
1241* 100000h F0000h E0000h
1242* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1243* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
1244* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1245* | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
1246* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1247* | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
1248* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
1249*****************************************************************************/
1250.macro AMD_ENABLE_STACK
1251
1252# These are local labels. Declared so linker doesn't cause 'redefined label' errors
1253 LOCAL SetupStack
1254 LOCAL Real16bMode
1255 LOCAL Protected32Mode
1256 LOCAL ClearTheStack
1257
1258# Note that SS:ESP will be default stack. Note that this stack
1259# routine will not be used after memory has been initialized. Because
1260# of its limited lifetime, it will not conflict with typical PCI devices.
1261 movd %ebx, %mm0 # Put return address in a safe place
1262 movd %ebp, %mm1 # Save some other user registers
1263
1264 # get node id and core id of current executing core
1265 GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
1266 # Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
1267
1268 # determine if stack is already enabled. We are using the DefType MSR for this determination.
1269 # It is =0 after reset; CAR setup sets it to enable the MTRRs
1270 mov %cr0, %eax
1271 test $CR0_MASK, %eax # Is cache disabled? (CD & NW bits)
1272 jnz SetupStack # Jump if yes
1273 mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
1274 _RDMSR
1275 test $MSR_MASK, %eax # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
1276 jz SetupStack # Jump if no
1277 or $FLAG_STACK_REENTRY, %esi # Bit25, indicate stack has already been initialized
1278
1279SetupStack:
1280 # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
1281 mov %esi, %ebx # Get my Node/Core info
1282 xor %bl, %bl
1283 shl $3, %bh # Isolate my node#, match alignment for PCI Dev#
1284 mov $0x8000C144, %eax # D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit
1285 add %bh, %ah
1286 mov %eax, %ebx # Save PCI address for Base/Limit pair
1287
1288 mov $0x0CF8, %dx
1289 out %eax, %dx
1290 add $4, %dx
1291 xor %eax, %eax # Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
1292 out %eax, %dx # DRAM Limit = node0, no interleave
1293
1294 mov %ebx, %eax
1295 sub $4, %eax # Now point to the Base register
1296 mov $0x0CF8, %dx
1297 out %eax, %dx
1298 add $4, %dx
1299 mov $0x00000003, %eax # Set the read and write enable bits
1300 out %eax, %dx # DRAM Base = 0x0000, R/W
1301
1302 AMD_ENABLE_STACK_FAMILY_HOOK
1303
1304 # Init CPU MSRs for our init routines
1305 mov $MTRR_SYS_CFG, %ecx # SYS_CFG
1306 _RDMSR
1307 bts $MTRR_FIX_DRAM_MOD_EN, %eax # Turn on modification enable bit
1308 _WRMSR
1309
1310 mov %esi, %eax
1311 bt $FLAG_STACK_REENTRY, %eax # Is this a 2nd entry?
1312 #.if (!carry?) # On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
1313 jc 0f
1314 bt $FLAG_IS_PRIMARY, %eax # Is this core the primary in a compute unit?
1315 #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
1316 # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
1317 # Clear all variable and Fixed MTRRs for non-shared cores
1318 jnc 0f
1319 mov $AMD_MTRR_VARIABLE_BASE0, %ecx
1320 xor %eax, %eax
1321 xor %edx, %edx
1322 #.while (cl != 10h) # Variable MTRRphysBase[n] and MTRRphysMask[n]
1323 jmp 1f
1324 2:
1325 _WRMSR
1326 inc %cl
1327 #.endw
1328 1:
1329 cmp $0x10, %cl
1330 jne 2b
1331 mov $AMD_MTRR_FIX64k_00000, %cx # MSR:0000_0250
1332 _WRMSR
1333 mov $AMD_MTRR_FIX16k_80000, %cx # MSR:0000_0258
1334 _WRMSR
1335 mov $AMD_MTRR_FIX16k_A0000, %cx # MSR:0000_0259
1336 _WRMSR
1337 mov $AMD_MTRR_FIX4k_C0000, %cx # Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
1338 #.while (cl != 70h)
1339 jmp 3f
1340 4:
1341 _WRMSR
1342 inc %cl
1343 #.endw
1344 3:
1345 cmp $0x70, %cl
1346 jne 4b
1347 # Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
1348 # - not strictly needed since the FixedMTRRs take presedence.
1349 mov $(16 * 1024 * 1024), %eax
1350 mov $TOP_MEM, %ecx # MSR:C001_001A
1351 _WRMSR
1352 #.endif # End Is_Primary
1353 #.endif # End Stack_ReEntry
1354 0:
1355 # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
1356 xor %eax, %eax
1357 xor %edx, %edx
1358 mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019
1359 #.while (cl != 1Ah)
1360 jmp 1f
1361 2:
1362 _WRMSR
1363 inc %cl
1364 #.endw
1365 1:
1366 cmp $0x1A, %cl
1367 jne 2b
1368 mov $TOP_MEM2, %ecx # MSR:C001_001D
1369 _WRMSR
1370
1371 # setup MTTRs for stacks
1372 # A speculative read can be generated by a speculative fetch mis-aligned in a code zone
1373 # or due to a data zone being interpreted as code. When a speculative read occurs outside a
1374 # controlled region (intentionally used by software), it could cause an unwanted cache eviction.
1375 # To prevent speculative reads from causing an eviction, the unused cache ranges are set
1376 # to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
1377 # Note: some core stack regions will share an MTRR since the control granularity is much
1378 # larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
1379 # space covered by the MTRR when parseling out cache space for the various uses. In some cases
1380 # this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
1381 #
1382 # Outcome of this block is that: (Note the MTRR map at the top of the file)
1383 # ebp - start address of stack block
1384 # ebx - [31:16] - MTRR MSR address
1385 # - [15:8] - slot# in MTRR register
1386 # - [7:0] - block size in #4K blocks
1387 # review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
1388 #
1389
1390 mov %si, %ax # Load node, core
1391 #.if (al == 0) # Is a core 0?
1392 or %al, %al
1393 jne 1f
1394 #.if (ah == 0) # Is Node 0? (BSP)
1395 or %ah, %ah
1396 jne 2f
1397 # Is BSP, assign a 64K stack
1398 mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx
1399 mov $BSP_STACK_BASE_ADDR, %ebp
1400 jmp 0f
1401 #.else # node 1 to 7, core0
1402 2:
1403 # Is a Core0 of secondary node, assign 16K stacks
1404 mov $AMD_MTRR_FIX16k_80000, %bx
1405 shl $16, %ebx #
1406 mov %ah, %bh # Node# is used as slot#
1407 mov $(CORE0_STACK_SIZE / 0x1000), %bl
1408 mov %ah, %al # Base = (Node# * Size)#
1409 mul %bl #
1410 movzx %ax, %eax #
1411 shl $12, %eax # Expand back to full byte count (* 4K)
1412 add $CORE0_STACK_BASE_ADDR, %eax
1413 mov %eax, %ebp
1414 #.endif
1415 jmp 0f
1416 #.else #core 1 thru core 7
1417 1:
1418 # Is core 1-7 of any node, assign 4K stacks
1419 mov $8, %al # CoreIndex = ( (Node# * 8) ...
1420 mul %ah #
1421 mov %si, %bx #
1422 add %bl, %al # ... + Core#)#
1423
1424 mov $AMD_MTRR_FIX64k_00000, %bx
1425 shl $16, %ebx #
1426 mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
1427 shr $4, %bh #
1428 add $4, %bh #
1429 mov $(CORE1_STACK_SIZE / 0x1000), %bl
1430
1431 mul %bl # Base = ( (CoreIndex * Size) ...
1432 movzx %ax, %eax #
1433 shl $12, %eax # Expand back to full byte count (* 4K)
1434 add $CORE1_STACK_BASE_ADDR, %eax # ... + Base_Addr)#
1435 mov %eax, %ebp
1436 #.endif
1437 0:
1438
1439 # Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
1440 mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot
1441 mov %bh, %cl # ShiftCount = ((slot# ...
1442 and $0x03, %cl # ... % 4) ...
1443 shl $0x03, %cl # ... * 8)#
1444 shl %cl, %edi # Cache type is now in correct position
1445 ror $16, %ebx # Get the MTRR address
1446 movzx %bx, %ecx #
1447 rol $16, %ebx # Put slot# & size back in BX
1448 _RDMSR # Read-modify-write the MSR
1449 #.if (bh < 4) # Is value in lower or upper half of MSR?
1450 cmp $4, %bh
1451 jae 1f
1452 or %edi, %eax #
1453 jmp 0f
1454 #.else
1455 1: #
1456 or %edi, %edx #
1457 #.endif #
1458 0:
1459 _WRMSR #
1460
1461 # Enable MTRR defaults as UC type
1462 mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
1463 _RDMSR # Read-modify-write the MSR
1464 bts $MTRR_DEF_TYPE_EN, %eax # MtrrDefTypeEn
1465 bts $MTRR_DEF_TYPE_FIX_EN, %eax # MtrrDefTypeFixEn
1466 _WRMSR
1467
1468 # Close the modification window on the Fixed MTRRs
1469 mov $MTRR_SYS_CFG, %ecx # MSR:0C001_0010
1470 _RDMSR
1471 bts $MTRR_FIX_DRAM_EN, %eax # MtrrFixDramEn
1472 bts $MTRR_VAR_DRAM_EN, %eax # variable MTRR enable bit
1473 btr $MTRR_FIX_DRAM_MOD_EN, %eax # Turn off modification enable bit
1474 _WRMSR
1475
1476 # Enable caching in CR0
1477 mov %cr0, %eax # Enable WT/WB cache
1478 btr $CR0_PG, %eax # Make sure paging is disabled
1479 btr $CR0_CD, %eax # Clear CR0 NW and CD
1480 btr $CR0_NW, %eax
1481 mov %eax, %cr0
1482
1483 # Use the Stack Base & size to calculate SS and ESP values
1484 # review:
1485 # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
1486 # ebp - start address of stack block
1487 # ebx - [31:16] - MTRR MSR address
1488 # - [15:8] - slot# in MTRR register
1489 # - [7:0] - block size in #4K blocks
1490 #
1491 mov %ebp, %esp # Initialize the stack pointer
1492 mov %esp, %edi # Copy the stack start to edi
1493 movzx %bl, %bx
1494 movzx %bx, %ebx # Clear upper ebx, don't need MSR addr anymore
1495 shl $12, %ebx # Make size full byte count (* 4K)
1496 add %ebx, %esp # Set the Stack Pointer as full linear address
1497 sub $4, %esp
1498 #
1499 # review:
1500 # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
1501 # edi - 32b start address of stack block
1502 # ebx - size of stack block
1503 # esp - 32b linear stack pointer
1504 #
1505
1506 # Determine mode for SS base;
1507 mov %cr0, %ecx # Check for 32-bit protect mode
1508 bt $CR0_PE, %ecx #
1509 #.if (!carry?) # PE=0 means real mode
1510 jc Protected32Mode
1511 mov %cs, %cx # PE=1
1512 cmp $0x0D000, %cx # Check for CS
1513 jb Protected32Mode # If CS < D000, it is a selector instead of a segment
1514 # alter SS:ESP for 16b Real Mode:
1515Real16bMode:
1516 mov %edi, %eax
1517 shr $4, %eax # Create a Real Mode segment for ss, ds, es
1518 mov %ax, %ss
1519 mov %ax, %ds
1520 mov %ax, %es
1521 shl $4, %eax
1522 sub %eax, %edi # Adjust the clearing pointer for Seg:Offset mode
1523 mov %ebx, %esp # Make SP an offset from SS
1524 sub $4, %esp #
1525 # .endif # endif
1526 # #else
1527 # Default is to use Protected 32b Mode
1528 #.endif
1529 ;
1530Protected32Mode:
1531 #
1532 # Clear The Stack
1533 # Now that we have set the location and the MTRRs, initialize the cache by
1534 # reading then writing to zero all of the stack area.
1535 # review:
1536 # ss - Stack base
1537 # esp - stack pointer
1538 # ebx - size of stack block
1539 # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
1540 # edi - address of start of stack block
1541 #
1542
1543ClearTheStack: # Stack base is in SS, stack pointer is in ESP
1544 shr $2, %ebx # ebx = stack block size in dwords
1545 mov %bx, %cx #
1546 # Check our flags - Don't clear an existing stack
1547 #.if ( !(esi & 0FF000000h)) # Check our flags
1548 test $(1 << FLAG_STACK_REENTRY), %esi
1549 jne 1f
1550 cld
1551 mov %edi, %esi
1552 rep lodsl (%esi) # Pre-load the range
1553 xor %eax, %eax
1554 mov %bx, %cx
1555 mov %edi, %esi # Preserve base for push on stack
1556 rep stosl (%edi) # Clear the range
1557 movl $0x0ABCDDCBA, (%esp) # Put marker in top stack dword
1558 shl $2, %ebx # Put stack size and base
1559 push %ebx # in top of stack
1560 push %esi
1561
1562 mov %ebx, %ecx # Return size of stack in bytes
1563 xor %eax, %eax # eax = 0 : no error return code
1564 jmp 0f
1565 #.else
1566 1:
1567 movzx %cx, %ecx
1568 shl $2, %ecx # Return size of stack in bytes
1569 mov %esi, %eax
1570 shr $24, %eax # Keep the flags as part of the error report
1571 or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
1572 #.endif
1573 0:
1574
1575 movd %mm0, %ebx # Restore return address
1576 movd %mm1, %ebp
1577.endm
1578
1579/*****************************************************************************
1580* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
1581* should only be executed on the BSP
1582*
1583* In:
1584* none
1585*
1586* Out:
1587* EAX = AGESA_SUCCESS
1588*
1589* Preserved:
1590* ebx
1591* Destroyed:
1592* eax, ecx, edx, esp
1593*****************************************************************************/
1594.macro AMD_DISABLE_STACK
1595
1596 mov %ebx, %esp # Save return address
1597
1598 # get node/core/flags of current executing core
1599 GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
1600
1601 # Turn on modification enable bit
1602 mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
1603 _RDMSR
1604 bts $MTRR_FIX_DRAM_MOD_EN, %eax # Enable modifications
1605 _WRMSR
1606
1607 # Set lower 640K MTRRs for Write-Back memory caching
1608 mov $AMD_MTRR_FIX64k_00000, %ecx
1609 mov $0x1E1E1E1E, %eax
1610 mov %eax, %edx
1611 _WRMSR # 0 - 512K = WB Mem
1612 mov $AMD_MTRR_FIX16k_80000, %ecx
1613 _WRMSR # 512K - 640K = WB Mem
1614
1615 # Turn off modification enable bit
1616 mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
1617 _RDMSR
1618 btr $MTRR_FIX_DRAM_MOD_EN, %eax # Disable modification
1619 _WRMSR
1620
1621 AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
1622
1623 mov %esp, %ebx
1624 xor %eax, %eax
1625
1626.endm
1627