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review.coreboot.org / coreboot / b2d68976c830c3b4eddf78ea788f02cfa6d25ffc / . / src / vendorcode / amd / agesa / f14 / AMD.h
blob: 5c77c58269191bbd2c8b3bd2bc8a12b18ee01c14 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Agesa structures and definitions
6 *
7 * Contains AMD AGESA core interface
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: Include
12 * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
13 */
14/*
15 *****************************************************************************
16 *
17 * Copyright (c) 2011, Advanced Micro Devices, Inc.
18 * All rights reserved.
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * ***************************************************************************
43 *
44 */
45
46
47#ifndef _AMD_H_
48#define _AMD_H_
49
50#define AGESA_REVISION "Arch2008"
51#define AGESA_ID "AGESA"
52
53#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
54#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
55//
56//
57// AGESA Types and Definitions
58//
59//
60#define LAST_ENTRY 0xFFFFFFFF
61#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
62#define IOCF8 0xCF8
63#define IOCFC 0xCFC
64
65/// The return status for all AGESA public services.
66///
67/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
68/// will have log entries with more detail.
69///
70typedef enum {
71 AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
72 AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
73 ///< Not logged.
74 AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
75 ///< Example, memory address not installed, heap buffer handle not found.
76 ///< Not Logged.
77 // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
78 AGESA_ALERT, ///< An observed condition, but no loss of function.
79 ///< See log. Example, HT CRC.
80 AGESA_WARNING, ///< Possible or minor loss of function. See Log.
81 AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
82 AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
83 AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
84 ///< may not be able to reliably produce log events.
85 AgesaStatusMax ///< Not a status, for limit checking.
86} AGESA_STATUS;
87
88/// For checking whether a status is at or above the mandatory log level.
89#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
90
91/**
92 * Callout method to the host environment.
93 *
94 * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
95 *
96 * @param[in] Function The specific callout function being invoked.
97 * @param[in] FcnData Function specific data item.
98 * @param[in,out] ConfigPtr Reference to Callout params.
99 */
100typedef AGESA_STATUS (*CALLOUT_ENTRY) (
101 IN UINT32 Function,
102 IN UINTN FcnData,
103 IN OUT VOID *ConfigPtr
104 );
105
106typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
107typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
108
109///This allocation type is used by the AmdCreateStruct entry point
110typedef enum {
111 PreMemHeap = 0, ///< Create heap in cache.
112 PostMemDram, ///< Create heap in memory.
113 ByHost ///< Create heap by Host.
114} ALLOCATION_METHOD;
115
116/// These width descriptors are used by the library function, and others, to specify the data size
117typedef enum ACCESS_WIDTH {
118 AccessWidth8 = 1, ///< Access width is 8 bits.
119 AccessWidth16, ///< Access width is 16 bits.
120 AccessWidth32, ///< Access width is 32 bits.
121 AccessWidth64, ///< Access width is 64 bits.
122
123 AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
124 AccessS3SaveWidth16, ///< Save 16 bits data.
125 AccessS3SaveWidth32, ///< Save 32 bits data.
126 AccessS3SaveWidth64, ///< Save 64 bits data.
127} ACCESS_WIDTH;
128
129/// AGESA struct name
130typedef enum {
131 // AGESA BASIC FUNCTIONS
132 AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
133 AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
134 AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
135 AMD_INIT_ENV, ///< AmdInitEnv entry point handle
136 AMD_INIT_LATE, ///< AmdInitLate entry point handle
137 AMD_INIT_MID, ///< AmdInitMid entry point handle
138 AMD_INIT_POST, ///< AmdInitPost entry point handle
139 AMD_INIT_RESET, ///< AmdInitReset entry point handle
140 AMD_INIT_RESUME, ///< AmdInitResume entry point handle
141 AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
142 AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
143 AMD_S3_SAVE, ///< AmdS3Save entry point handle
144 AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
145 AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
146 AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
147 AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
148 AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
149 AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
150 AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
151} AGESA_STRUCT_NAME;
152
153 /* ResetType constant values */
154#define WARM_RESET_WHENEVER 1
155#define COLD_RESET_WHENEVER 2
156#define WARM_RESET_IMMEDIATELY 3
157#define COLD_RESET_IMMEDIATELY 4
158
159
160// AGESA Structures
161
162/// The standard header for all AGESA services.
163/// For internal AGESA naming conventions, see @ref amdconfigparamname .
164typedef struct {
165 IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
166 IN UINT32 Func; ///< The service desired
167 IN UINT32 AltImageBasePtr; ///< Alternate Image location
168 IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
169 IN UINT8 HeapStatus; ///< For heap status from boot time slide.
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]170 IN VOID *HeapBasePtr; ///< Location of the heap
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]171 IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
172} AMD_CONFIG_PARAMS;
173
174
175/// Create Struct Interface.
176typedef struct {
177 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
178 IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
179 IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
180 IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
181 IN OUT VOID *NewStructPtr; ///< The struct for the service.
182 ///< The struct to init for ByHost allocation,
183 ///< the initialized struct on return.
184} AMD_INTERFACE_PARAMS;
185
186#define FUNC_0 0 // bit-placed for PCI address creation
187#define FUNC_1 1
188#define FUNC_2 2
189#define FUNC_3 3
190#define FUNC_4 4
191#define FUNC_5 5
192#define FUNC_6 6
193#define FUNC_7 7
194
195/// AGESA Binary module header structure
196typedef struct {
197 IN UINT32 Signature; ///< Binary Signature
198 IN CHAR8 CreatorID[8]; ///< 8 characters ID
199 IN CHAR8 Version[12]; ///< 12 characters version
200 IN UINT32 ModuleInfoOffset; ///< Offset of module
201 IN UINT32 EntryPointAddress; ///< Entry address
202 IN UINT32 ImageBase; ///< Image base
203 IN UINT32 RelocTableOffset; ///< Relocate Table offset
204 IN UINT32 ImageSize; ///< Size
205 IN UINT16 Checksum; ///< Checksum
206 IN UINT8 ImageType; ///< Type
207 IN UINT8 V_Reserved; ///< Reserved
208} AMD_IMAGE_HEADER;
209/// AGESA Binary module header structure
210typedef struct _AMD_MODULE_HEADER {
211 IN UINT32 ModuleHeaderSignature; ///< Module signature
212 IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
213 IN CHAR8 ModuleVersion[12]; ///< 12 characters version
214 IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
215 IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
216} AMD_MODULE_HEADER;
217
218// AMD_CODE_HEADER Signatures.
219#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
220#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
221#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
222
223/// AGESA_CODE_SIGNATURE
224typedef struct {
225 IN CHAR8 Signature[8]; ///< code header Signature
226 IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
227 IN CHAR8 Version[12]; ///< 12 character version string
228 IN CHAR8 TerminatorNull; ///< null terminated string
229 IN CHAR8 VerReserved[7]; ///< reserved space
230} AMD_CODE_HEADER;
231
232/// Extended PCI address format
233typedef struct {
234 IN OUT UINT32 Register:12; ///< Register offset
235 IN OUT UINT32 Function:3; ///< Function number
236 IN OUT UINT32 Device:5; ///< Device number
237 IN OUT UINT32 Bus:8; ///< Bus number
238 IN OUT UINT32 Segment:4; ///< Segment
239} EXT_PCI_ADDR;
240
241/// Union type for PCI address
242typedef union _PCI_ADDR {
243 IN UINT32 AddressValue; ///< Formal address
244 IN EXT_PCI_ADDR Address; ///< Extended address
245} PCI_ADDR;
246
247// SBDFO - Segment Bus Device Function Offset
248// 31:28 Segment (4-bits)
249// 27:20 Bus (8-bits)
250// 19:15 Device (5-bits)
251// 14:12 Function(3-bits)
252// 11:00 Offset (12-bits)
253
254#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
255 (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
256#define ILLEGAL_SBDFO 0xFFFFFFFF
257
258/// CPUID data received registers format
259typedef struct {
260 OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
261 OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
262 OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
263 OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
264} CPUID_DATA;
265
266/// HT frequency for external callbacks
267typedef enum {
268 HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
269 HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
270 HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
271 HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
272 HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
273 HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
274 HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
275 HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
276 HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
277 HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
278 HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
279 HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
280 HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
281 HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
282 HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
283 HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
284 HT_FREQUENCY_MAX ///< Limit check.
285} HT_FREQUENCIES;
286// The minimum HT3 frequency
287#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
288
289#ifndef BIT0
290 #define BIT0 0x0000000000000001ull
291#endif
292#ifndef BIT1
293 #define BIT1 0x0000000000000002ull
294#endif
295#ifndef BIT2
296 #define BIT2 0x0000000000000004ull
297#endif
298#ifndef BIT3
299 #define BIT3 0x0000000000000008ull
300#endif
301#ifndef BIT4
302 #define BIT4 0x0000000000000010ull
303#endif
304#ifndef BIT5
305 #define BIT5 0x0000000000000020ull
306#endif
307#ifndef BIT6
308 #define BIT6 0x0000000000000040ull
309#endif
310#ifndef BIT7
311 #define BIT7 0x0000000000000080ull
312#endif
313#ifndef BIT8
314 #define BIT8 0x0000000000000100ull
315#endif
316#ifndef BIT9
317 #define BIT9 0x0000000000000200ull
318#endif
319#ifndef BIT10
320 #define BIT10 0x0000000000000400ull
321#endif
322#ifndef BIT11
323 #define BIT11 0x0000000000000800ull
324#endif
325#ifndef BIT12
326 #define BIT12 0x0000000000001000ull
327#endif
328#ifndef BIT13
329 #define BIT13 0x0000000000002000ull
330#endif
331#ifndef BIT14
332 #define BIT14 0x0000000000004000ull
333#endif
334#ifndef BIT15
335 #define BIT15 0x0000000000008000ull
336#endif
337#ifndef BIT16
338 #define BIT16 0x0000000000010000ull
339#endif
340#ifndef BIT17
341 #define BIT17 0x0000000000020000ull
342#endif
343#ifndef BIT18
344 #define BIT18 0x0000000000040000ull
345#endif
346#ifndef BIT19
347 #define BIT19 0x0000000000080000ull
348#endif
349#ifndef BIT20
350 #define BIT20 0x0000000000100000ull
351#endif
352#ifndef BIT21
353 #define BIT21 0x0000000000200000ull
354#endif
355#ifndef BIT22
356 #define BIT22 0x0000000000400000ull
357#endif
358#ifndef BIT23
359 #define BIT23 0x0000000000800000ull
360#endif
361#ifndef BIT24
362 #define BIT24 0x0000000001000000ull
363#endif
364#ifndef BIT25
365 #define BIT25 0x0000000002000000ull
366#endif
367#ifndef BIT26
368 #define BIT26 0x0000000004000000ull
369#endif
370#ifndef BIT27
371 #define BIT27 0x0000000008000000ull
372#endif
373#ifndef BIT28
374 #define BIT28 0x0000000010000000ull
375#endif
376#ifndef BIT29
377 #define BIT29 0x0000000020000000ull
378#endif
379#ifndef BIT30
380 #define BIT30 0x0000000040000000ull
381#endif
382#ifndef BIT31
383 #define BIT31 0x0000000080000000ull
384#endif
385#ifndef BIT32
386 #define BIT32 0x0000000100000000ull
387#endif
388#ifndef BIT33
389 #define BIT33 0x0000000200000000ull
390#endif
391#ifndef BIT34
392 #define BIT34 0x0000000400000000ull
393#endif
394#ifndef BIT35
395 #define BIT35 0x0000000800000000ull
396#endif
397#ifndef BIT36
398 #define BIT36 0x0000001000000000ull
399#endif
400#ifndef BIT37
401 #define BIT37 0x0000002000000000ull
402#endif
403#ifndef BIT38
404 #define BIT38 0x0000004000000000ull
405#endif
406#ifndef BIT39
407 #define BIT39 0x0000008000000000ull
408#endif
409#ifndef BIT40
410 #define BIT40 0x0000010000000000ull
411#endif
412#ifndef BIT41
413 #define BIT41 0x0000020000000000ull
414#endif
415#ifndef BIT42
416 #define BIT42 0x0000040000000000ull
417#endif
418#ifndef BIT43
419 #define BIT43 0x0000080000000000ull
420#endif
421#ifndef BIT44
422 #define BIT44 0x0000100000000000ull
423#endif
424#ifndef BIT45
425 #define BIT45 0x0000200000000000ull
426#endif
427#ifndef BIT46
428 #define BIT46 0x0000400000000000ull
429#endif
430#ifndef BIT47
431 #define BIT47 0x0000800000000000ull
432#endif
433#ifndef BIT48
434 #define BIT48 0x0001000000000000ull
435#endif
436#ifndef BIT49
437 #define BIT49 0x0002000000000000ull
438#endif
439#ifndef BIT50
440 #define BIT50 0x0004000000000000ull
441#endif
442#ifndef BIT51
443 #define BIT51 0x0008000000000000ull
444#endif
445#ifndef BIT52
446 #define BIT52 0x0010000000000000ull
447#endif
448#ifndef BIT53
449 #define BIT53 0x0020000000000000ull
450#endif
451#ifndef BIT54
452 #define BIT54 0x0040000000000000ull
453#endif
454#ifndef BIT55
455 #define BIT55 0x0080000000000000ull
456#endif
457#ifndef BIT56
458 #define BIT56 0x0100000000000000ull
459#endif
460#ifndef BIT57
461 #define BIT57 0x0200000000000000ull
462#endif
463#ifndef BIT58
464 #define BIT58 0x0400000000000000ull
465#endif
466#ifndef BIT59
467 #define BIT59 0x0800000000000000ull
468#endif
469#ifndef BIT60
470 #define BIT60 0x1000000000000000ull
471#endif
472#ifndef BIT61
473 #define BIT61 0x2000000000000000ull
474#endif
475#ifndef BIT62
476 #define BIT62 0x4000000000000000ull
477#endif
478#ifndef BIT63
479 #define BIT63 0x8000000000000000ull
480#endif
481
482#endif // _AMD_H_