Lee Leahy | 37b5ef2 | 2016-07-31 14:15:49 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <console/console.h> |
| 15 | #include <fsp/util.h> |
| 16 | |
| 17 | void fsp_print_header_info(const struct fsp_header *hdr) |
| 18 | { |
| 19 | union { |
| 20 | uint32_t val; |
| 21 | struct { |
| 22 | uint8_t bld_num; |
| 23 | uint8_t revision; |
| 24 | uint8_t minor; |
| 25 | uint8_t major; |
| 26 | } rev; |
| 27 | } revision; |
| 28 | |
| 29 | revision.val = hdr->fsp_revision; |
| 30 | |
Lee Leahy | b2b97a5 | 2017-03-10 08:40:18 -0800 | [diff] [blame^] | 31 | printk(BIOS_SPEW, "Spec version: v%u.%u\n", (hdr->spec_version >> 4), |
Lee Leahy | 37b5ef2 | 2016-07-31 14:15:49 -0700 | [diff] [blame] | 32 | hdr->spec_version & 0xf); |
| 33 | printk(BIOS_SPEW, "Revision: %u.%u.%u, Build Number %u\n", |
| 34 | revision.rev.major, |
| 35 | revision.rev.minor, |
| 36 | revision.rev.revision, |
| 37 | revision.rev.bld_num); |
| 38 | printk(BIOS_SPEW, "Type: %s/%s\n", |
Lee Leahy | b2b97a5 | 2017-03-10 08:40:18 -0800 | [diff] [blame^] | 39 | (hdr->component_attribute & 1) ? "release" : "debug", |
| 40 | (hdr->component_attribute & 2) ? "test" : "official"); |
Lee Leahy | 37b5ef2 | 2016-07-31 14:15:49 -0700 | [diff] [blame] | 41 | printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n", |
| 42 | hdr->image_id, hdr->image_base, hdr->image_size); |
| 43 | printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n", |
| 44 | hdr->cfg_region_offset, hdr->cfg_region_size); |
| 45 | |
| 46 | if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { |
| 47 | printk(BIOS_SPEW, "\tMemory init offset 0x%zx\n", |
| 48 | hdr->memory_init_entry_offset); |
| 49 | } |
| 50 | |
| 51 | if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { |
| 52 | printk(BIOS_SPEW, "\tSilicon init offset 0x%zx\n", |
| 53 | hdr->silicon_init_entry_offset); |
| 54 | printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n", |
| 55 | hdr->notify_phase_entry_offset); |
| 56 | } |
| 57 | |
| 58 | } |