Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <arch/romstage.h> |
| 4 | #include <cbmem.h> |
Subrata Banik | b53e27b | 2023-01-16 17:04:09 +0530 | [diff] [blame] | 5 | #include <cf9_reset.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 6 | #include <console/console.h> |
Tarun Tuli | eed31cb | 2023-01-31 18:14:35 +0000 | [diff] [blame] | 7 | #include <elog.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 8 | #include <fsp/util.h> |
| 9 | #include <intelblocks/cfg.h> |
| 10 | #include <intelblocks/cse.h> |
Jeremy Compostella | 1f4d7c7 | 2023-01-04 09:41:52 -0700 | [diff] [blame] | 11 | #include <intelblocks/early_graphics.h> |
Subrata Banik | b53e27b | 2023-01-16 17:04:09 +0530 | [diff] [blame] | 12 | #include <intelblocks/pcr.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 13 | #include <intelblocks/pmclib.h> |
Angel Pons | 53496e6 | 2021-02-19 20:38:37 +0100 | [diff] [blame] | 14 | #include <intelblocks/smbus.h> |
Subrata Banik | b2e8bd8 | 2021-11-17 15:35:05 +0530 | [diff] [blame] | 15 | #include <intelblocks/thermal.h> |
Michał Żygowski | c7fee24 | 2022-10-15 16:39:46 +0200 | [diff] [blame] | 16 | #include <intelblocks/vtd.h> |
Sridhar Siricilla | f5e94b6 | 2022-03-08 23:39:20 +0530 | [diff] [blame] | 17 | #include <intelbasecode/debug_feature.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 18 | #include <memory_info.h> |
| 19 | #include <soc/intel/common/smbios.h> |
| 20 | #include <soc/iomap.h> |
| 21 | #include <soc/pm.h> |
| 22 | #include <soc/romstage.h> |
| 23 | #include <soc/soc_chip.h> |
Krishna Prasad Bhat | 9eb7070 | 2021-12-02 10:30:26 +0530 | [diff] [blame] | 24 | #include <cpu/intel/cpu_ids.h> |
Sridhar Siricilla | b647e35 | 2021-12-01 14:33:25 +0530 | [diff] [blame] | 25 | #include <timestamp.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 26 | #include <string.h> |
Subrata Banik | c8b840f | 2022-12-31 14:47:55 +0530 | [diff] [blame] | 27 | #include <security/intel/txt/txt.h> |
Subrata Banik | b53e27b | 2023-01-16 17:04:09 +0530 | [diff] [blame] | 28 | #include <soc/pcr_ids.h> |
| 29 | |
| 30 | #define PSF_UFS0_BASE_ADDRESS 0x280 |
| 31 | #define PSF_UFS1_BASE_ADDRESS 0x300 |
| 32 | #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |
| 33 | #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) |
| 34 | |
| 35 | static void disable_ufs(void) |
| 36 | { |
| 37 | /* disable USF0 */ |
| 38 | pcr_or32(PID_PSF2, PSF_UFS0_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, |
| 39 | PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); |
| 40 | |
| 41 | /* disable USF1 */ |
| 42 | pcr_or32(PID_PSF2, PSF_UFS1_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, |
| 43 | PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); |
| 44 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 45 | |
Jeremy Compostella | e3884a1 | 2023-01-19 11:41:30 -0700 | [diff] [blame] | 46 | #include "ux.h" |
| 47 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 48 | #define FSP_SMBIOS_MEMORY_INFO_GUID \ |
| 49 | { \ |
| 50 | 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ |
| 51 | 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ |
| 52 | } |
| 53 | |
Krishna Prasad Bhat | 9eb7070 | 2021-12-02 10:30:26 +0530 | [diff] [blame] | 54 | bool skip_cse_sub_part_update(void) |
| 55 | { |
Lean Sheng Tan | 9e78dd1 | 2022-04-01 12:03:51 +0200 | [diff] [blame] | 56 | return cpu_get_cpuid() != CPUID_ALDERLAKE_K0; |
Krishna Prasad Bhat | 9eb7070 | 2021-12-02 10:30:26 +0530 | [diff] [blame] | 57 | } |
| 58 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 59 | /* Save the DIMM information for SMBIOS table 17 */ |
| 60 | static void save_dimm_info(void) |
| 61 | { |
| 62 | int node, channel, dimm, dimm_max, index; |
| 63 | size_t hob_size; |
| 64 | const CONTROLLER_INFO *ctrlr_info; |
| 65 | const CHANNEL_INFO *channel_info; |
| 66 | const DIMM_INFO *src_dimm; |
| 67 | struct dimm_info *dest_dimm; |
| 68 | struct memory_info *mem_info; |
| 69 | const MEMORY_INFO_DATA_HOB *meminfo_hob; |
| 70 | const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID; |
| 71 | const uint8_t *serial_num; |
| 72 | const char *dram_part_num = NULL; |
Nick Vaccaro | 0ed02d0 | 2020-09-30 09:49:05 -0700 | [diff] [blame] | 73 | size_t dram_part_num_len = 0; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 74 | |
| 75 | /* Locate the memory info HOB, presence validated by raminit */ |
| 76 | meminfo_hob = fsp_find_extension_hob_by_guid( |
| 77 | smbios_memory_info_guid, |
| 78 | &hob_size); |
| 79 | if (meminfo_hob == NULL || hob_size == 0) { |
| 80 | printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); |
| 81 | return; |
| 82 | } |
| 83 | |
| 84 | /* |
| 85 | * Allocate CBMEM area for DIMM information used to populate SMBIOS |
| 86 | * table 17 |
| 87 | */ |
| 88 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 89 | if (mem_info == NULL) { |
| 90 | printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); |
| 91 | return; |
| 92 | } |
| 93 | memset(mem_info, 0, sizeof(*mem_info)); |
| 94 | |
| 95 | /* Allow mainboard to override DRAM part number. */ |
Nick Vaccaro | 0ed02d0 | 2020-09-30 09:49:05 -0700 | [diff] [blame] | 96 | dram_part_num = mainboard_get_dram_part_num(); |
| 97 | if (dram_part_num) |
| 98 | dram_part_num_len = strlen(dram_part_num); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 99 | |
| 100 | /* Save available DIMM information */ |
| 101 | index = 0; |
| 102 | dimm_max = ARRAY_SIZE(mem_info->dimm); |
| 103 | for (node = 0; node < MAX_NODE; node++) { |
| 104 | ctrlr_info = &meminfo_hob->Controller[node]; |
| 105 | for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { |
| 106 | channel_info = &ctrlr_info->ChannelInfo[channel]; |
| 107 | if (channel_info->Status != CHANNEL_PRESENT) |
| 108 | continue; |
| 109 | |
| 110 | for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { |
| 111 | src_dimm = &channel_info->DimmInfo[dimm]; |
| 112 | dest_dimm = &mem_info->dimm[index]; |
| 113 | if (src_dimm->Status != DIMM_PRESENT) |
| 114 | continue; |
| 115 | |
| 116 | /* If there is no DRAM part number overridden by |
| 117 | * mainboard then use original one. */ |
| 118 | if (!dram_part_num) { |
| 119 | dram_part_num_len = sizeof(src_dimm->ModulePartNum); |
| 120 | dram_part_num = (const char *) |
| 121 | &src_dimm->ModulePartNum[0]; |
| 122 | } |
| 123 | |
| 124 | uint8_t memProfNum = meminfo_hob->MemoryProfile; |
| 125 | serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; |
| 126 | |
| 127 | /* Populate the DIMM information */ |
| 128 | dimm_info_fill(dest_dimm, |
| 129 | src_dimm->DimmCapacity, |
| 130 | meminfo_hob->MemoryType, |
| 131 | meminfo_hob->ConfiguredMemoryClockSpeed, |
| 132 | src_dimm->RankInDimm, |
| 133 | channel_info->ChannelId, |
| 134 | src_dimm->DimmId, |
| 135 | dram_part_num, |
| 136 | dram_part_num_len, |
| 137 | serial_num, |
| 138 | meminfo_hob->DataWidth, |
| 139 | meminfo_hob->VddVoltage[memProfNum], |
| 140 | meminfo_hob->EccSupport, |
| 141 | src_dimm->MfgId, |
David Milosevic | 6be82a4 | 2022-10-18 19:17:19 +0200 | [diff] [blame] | 142 | src_dimm->SpdModuleType, |
Eric Lai | b15946d | 2023-06-13 10:21:58 +0800 | [diff] [blame^] | 143 | node, |
| 144 | meminfo_hob->MaximumMemoryClockSpeed); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 145 | index++; |
| 146 | } |
| 147 | } |
| 148 | } |
| 149 | mem_info->dimm_cnt = index; |
| 150 | printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); |
| 151 | } |
| 152 | |
Jeremy Compostella | e3884a1 | 2023-01-19 11:41:30 -0700 | [diff] [blame] | 153 | void cse_fw_update_misc_oper(void) |
| 154 | { |
Tarun Tuli | eed31cb | 2023-01-31 18:14:35 +0000 | [diff] [blame] | 155 | if (ux_inform_user_of_update_operation("CSE update")) |
| 156 | elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); |
Jeremy Compostella | e3884a1 | 2023-01-19 11:41:30 -0700 | [diff] [blame] | 157 | } |
| 158 | |
| 159 | void cse_board_reset(void) |
| 160 | { |
| 161 | early_graphics_stop(); |
| 162 | } |
| 163 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 164 | void mainboard_romstage_entry(void) |
| 165 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 166 | struct chipset_power_state *ps = pmc_get_power_state(); |
Subrata Banik | 55812d6 | 2023-01-16 13:24:47 +0530 | [diff] [blame] | 167 | bool s3wake = pmc_fill_power_state(ps) == ACPI_S3; |
| 168 | |
| 169 | /* Initialize HECI interface */ |
| 170 | cse_init(HECI1_BASE_ADDRESS); |
| 171 | |
| 172 | if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) |
| 173 | dbg_feature_cntrl_init(); |
| 174 | |
Jeremy Compostella | e3884a1 | 2023-01-19 11:41:30 -0700 | [diff] [blame] | 175 | /* |
| 176 | * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`. |
| 177 | * |
| 178 | * It would help to access VGA framebuffer prior calling into CSE |
| 179 | * firmware update or FSP-M. |
| 180 | */ |
| 181 | if (!CONFIG(INTEL_TXT)) |
| 182 | disable_intel_txt(); |
| 183 | |
Subrata Banik | 5ff0118 | 2023-04-20 11:08:17 +0530 | [diff] [blame] | 184 | if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) |
Subrata Banik | 55812d6 | 2023-01-16 13:24:47 +0530 | [diff] [blame] | 185 | cse_fw_sync(); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 186 | |
Subrata Banik | b53e27b | 2023-01-16 17:04:09 +0530 | [diff] [blame] | 187 | /* Program to Disable UFS Controllers */ |
| 188 | if (!is_devfn_enabled(PCH_DEVFN_UFS) && |
| 189 | (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) { |
| 190 | printk(BIOS_INFO, "Disabling UFS controllers\n"); |
| 191 | disable_ufs(); |
| 192 | if (ps->prev_sleep_state == ACPI_S5) { |
| 193 | printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n"); |
| 194 | system_reset(); |
| 195 | } |
| 196 | } |
| 197 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 198 | /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ |
| 199 | systemagent_early_init(); |
Angel Pons | 53496e6 | 2021-02-19 20:38:37 +0100 | [diff] [blame] | 200 | /* Program SMBus base address and enable it */ |
| 201 | smbus_common_init(); |
Subrata Banik | 55812d6 | 2023-01-16 13:24:47 +0530 | [diff] [blame] | 202 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 203 | |
Bora Guvendik | 860672e | 2021-09-26 17:25:48 -0700 | [diff] [blame] | 204 | /* Update coreboot timestamp table with CSE timestamps */ |
| 205 | if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) |
| 206 | cse_get_telemetry_data(); |
| 207 | |
Subrata Banik | b2e8bd8 | 2021-11-17 15:35:05 +0530 | [diff] [blame] | 208 | /* |
| 209 | * Set low maximum temp threshold value used for dynamic thermal sensor |
| 210 | * shutdown consideration. |
| 211 | * |
| 212 | * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the |
| 213 | * thermal sensor when CPU is in a C-state and LTT >= DTS Temp. |
| 214 | */ |
| 215 | pch_thermal_configuration(); |
| 216 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 217 | fsp_memory_init(s3wake); |
| 218 | pmc_set_disb(); |
Sridhar Siricilla | 248dbe0 | 2021-06-10 22:25:48 +0530 | [diff] [blame] | 219 | if (!s3wake) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 220 | save_dimm_info(); |
Jeremy Compostella | 1f4d7c7 | 2023-01-04 09:41:52 -0700 | [diff] [blame] | 221 | |
| 222 | /* |
| 223 | * Turn-off early graphics configuration with two purposes: |
| 224 | * - Clear any potentially still on-screen message |
| 225 | * - Allow PEIM graphics driver to smoothly execute in ramstage if |
| 226 | * RUN_FSP_GOP is selected |
| 227 | */ |
| 228 | early_graphics_stop(); |
Michał Żygowski | c7fee24 | 2022-10-15 16:39:46 +0200 | [diff] [blame] | 229 | |
| 230 | if (CONFIG(ENABLE_EARLY_DMA_PROTECTION)) |
| 231 | vtd_enable_dma_protection(); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 232 | } |