| Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| Stefan Reinauer | eca92fb | 2006-08-23 14:28:37 +0000 | [diff] [blame] | 2 | |
| Uwe Hermann | c70e9fc | 2010-02-15 23:10:19 +0000 | [diff] [blame] | 3 | /* |
| 4 | * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register |
| 5 | */ |
| 6 | |
| Stefan Reinauer | eca92fb | 2006-08-23 14:28:37 +0000 | [diff] [blame] | 7 | #ifndef __SDRAMMODE_H_DEFINED |
| 8 | #define __SDRAMMODE_H_DEFINED |
| 9 | |
| 10 | // SDRAM Mode Register definitions, per JESD79D |
| 11 | // These are transmitted via A0-A13 |
| 12 | |
| 13 | // Burst length |
| 14 | #define SDRAM_BURST_2 (1<<0) |
| 15 | #define SDRAM_BURST_4 (2<<0) |
| 16 | #define SDRAM_BURST_8 (3<<0) |
| 17 | |
| 18 | #define SDRAM_BURST_SEQUENTIAL (0<<3) |
| 19 | #define SDRAM_BURST_INTERLEAVED (1<<3) |
| 20 | |
| 21 | #define SDRAM_CAS_2_0 (2<<4) |
| 22 | #define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */ |
| 23 | #define SDRAM_CAS_1_5 (5<<4) /* Optional */ |
| 24 | #define SDRAM_CAS_2_5 (6<<4) |
| 25 | #define SDRAM_CAS_MASK (7<<4) |
| 26 | |
| 27 | #define SDRAM_MODE_NORMAL (0 << 7) |
| 28 | #define SDRAM_MODE_TEST (1 << 7) |
| 29 | #define SDRAM_MODE_DLL_RESET (2 << 7) |
| 30 | |
| 31 | // Extended Mode Register |
| 32 | |
| 33 | #define SDRAM_EXTMODE_DLL_ENABLE (0 << 0) |
| 34 | #define SDRAM_EXTMODE_DLL_DISABLE (1 << 0) |
| 35 | |
| 36 | #define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1) |
| 37 | #define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */ |
| 38 | |
| Lee Leahy | 84d20d0 | 2017-03-07 15:00:18 -0800 | [diff] [blame] | 39 | #endif // __SDRAMMODE_H_DEFINED |