Chris Ching | b146931 | 2016-05-11 09:06:50 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #ifndef ADI_RCC_DFF_GPIO_H |
| 17 | #define ADI_RCC_DFF_GPIO_H |
| 18 | |
| 19 | #include <southbridge/intel/fsp_rangeley/gpio.h> |
| 20 | |
| 21 | /* Core GPIO */ |
| 22 | const struct soc_gpio soc_gpio_mode = { |
| 23 | .gpio15 = GPIO_MODE_GPIO, /* Board ID GPIO */ |
| 24 | .gpio17 = GPIO_MODE_GPIO, /* Board ID GPIO */ |
| 25 | }; |
| 26 | |
| 27 | const struct soc_gpio soc_gpio_direction = { |
| 28 | .gpio15 = GPIO_DIR_INPUT, /* Board ID GPIO */ |
| 29 | .gpio17 = GPIO_DIR_INPUT, /* Board ID GPIO */ |
| 30 | }; |
| 31 | |
| 32 | const struct soc_gpio soc_gpio_level = { |
| 33 | }; |
| 34 | |
| 35 | const struct soc_gpio soc_gpio_tpe = { |
| 36 | }; |
| 37 | |
| 38 | const struct soc_gpio soc_gpio_tne = { |
| 39 | }; |
| 40 | |
| 41 | const struct soc_gpio soc_gpio_ts = { |
| 42 | }; |
| 43 | |
| 44 | /* Keep the CFIO struct in register order, not gpio order. */ |
| 45 | const struct soc_cfio soc_cfio_core[] = { |
| 46 | { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_28 */ |
| 47 | { 0x8000, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_27 */ |
| 48 | { 0x8500, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_26 */ |
| 49 | { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_21 */ |
| 50 | { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_22 */ |
| 51 | { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_23 */ |
| 52 | { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_25 */ |
| 53 | { 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_24 */ |
| 54 | { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_19 */ |
| 55 | { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_20 */ |
| 56 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_18 */ |
| 57 | { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_17 */ |
| 58 | { 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_7 */ |
| 59 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_4 */ |
| 60 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_5 */ |
| 61 | { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_6 */ |
| 62 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_1 */ |
| 63 | { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_2 */ |
| 64 | { 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_3 */ |
| 65 | { 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_0 */ |
| 66 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 67 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_10 */ |
| 68 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_13 */ |
| 69 | { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_14 */ |
| 70 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_11 */ |
| 71 | { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_8 */ |
| 72 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_9 */ |
| 73 | { 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_12 */ |
| 74 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_29 */ |
| 75 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_30 */ |
| 76 | { 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_15 */ |
| 77 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_16 */ |
| 78 | }; |
| 79 | |
| 80 | /* SUS GPIO */ |
| 81 | const struct soc_gpio soc_gpio_sus_mode = { |
| 82 | .gpio2 = GPIO_MODE_GPIO, |
| 83 | }; |
| 84 | |
| 85 | const struct soc_gpio soc_gpio_sus_direction = { |
| 86 | .gpio2 = GPIO_DIR_INPUT, |
| 87 | }; |
| 88 | |
| 89 | const struct soc_gpio soc_gpio_sus_level = { |
| 90 | }; |
| 91 | |
| 92 | const struct soc_gpio soc_gpio_sus_tpe = { |
| 93 | }; |
| 94 | |
| 95 | const struct soc_gpio soc_gpio_sus_tne = { |
| 96 | }; |
| 97 | |
| 98 | const struct soc_gpio soc_gpio_sus_ts = { |
| 99 | }; |
| 100 | |
| 101 | const struct soc_gpio soc_gpio_sus_we = { |
| 102 | }; |
| 103 | |
| 104 | |
| 105 | /* Keep the CFIO struct in register order, not gpio order. */ |
| 106 | const struct soc_cfio soc_cfio_sus[] = { |
| 107 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_21 */ |
| 108 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_20 */ |
| 109 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_19 */ |
| 110 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_22 */ |
| 111 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_17 */ |
| 112 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_18 */ |
| 113 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 114 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 115 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 116 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_14 */ |
| 117 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_13 */ |
| 118 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_15 */ |
| 119 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_16 */ |
| 120 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_25 */ |
| 121 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_24 */ |
| 122 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_26 */ |
| 123 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_27 */ |
| 124 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_23 */ |
| 125 | { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_2 */ |
| 126 | { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_1 */ |
| 127 | { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_7 */ |
| 128 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 129 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 130 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_3 */ |
| 131 | { 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_0 */ |
| 132 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 133 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 134 | { 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_12 */ |
| 135 | { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_6 */ |
| 136 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_10 */ |
| 137 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_9 */ |
| 138 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_8 */ |
| 139 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 140 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 141 | { 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_4 */ |
| 142 | { 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_11 */ |
| 143 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 144 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 145 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 146 | { 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */ |
| 147 | { 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_5 */ |
| 148 | }; |
| 149 | |
| 150 | const struct soc_gpio_map gpio_map = { |
| 151 | .core = { |
| 152 | .mode = &soc_gpio_mode, |
| 153 | .direction = &soc_gpio_direction, |
| 154 | .level = &soc_gpio_level, |
| 155 | .tpe = &soc_gpio_tpe, |
| 156 | .tne = &soc_gpio_tne, |
| 157 | .ts = &soc_gpio_ts, |
| 158 | .cfio_init = &soc_cfio_core[0], |
| 159 | .cfio_entrynum = sizeof(soc_cfio_core) / sizeof(struct soc_cfio), |
| 160 | }, |
| 161 | .sus = { |
| 162 | .mode = &soc_gpio_sus_mode, |
| 163 | .direction = &soc_gpio_sus_direction, |
| 164 | .level = &soc_gpio_sus_level, |
| 165 | .tpe = &soc_gpio_sus_tpe, |
| 166 | .tne = &soc_gpio_sus_tne, |
| 167 | .ts = &soc_gpio_sus_ts, |
| 168 | .we = &soc_gpio_sus_we, |
| 169 | .cfio_init = &soc_cfio_sus[0], |
| 170 | .cfio_entrynum = sizeof(soc_cfio_sus) / sizeof(struct soc_cfio), |
| 171 | }, |
| 172 | }; |
| 173 | |
| 174 | #endif /* ADI_RCC_DFF_GPIO_H */ |