Chris Ching | b146931 | 2016-05-11 09:06:50 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <types.h> |
| 18 | #include <string.h> |
| 19 | #include <cbmem.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/acpi.h> |
| 22 | #include <arch/ioapic.h> |
| 23 | #include <arch/acpigen.h> |
| 24 | #include <arch/smp/mpspec.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <cpu/x86/msr.h> |
| 29 | #include <southbridge/intel/fsp_rangeley/nvs.h> |
| 30 | #include <northbridge/intel/fsp_rangeley/northbridge.h> |
| 31 | |
| 32 | static global_nvs_t *gnvs_; |
| 33 | |
| 34 | void acpi_create_gnvs(global_nvs_t *gnvs) |
| 35 | { |
| 36 | gnvs_ = gnvs; |
| 37 | memset((void *)gnvs, 0, sizeof(*gnvs)); |
| 38 | gnvs->apic = 1; |
| 39 | gnvs->mpen = 1; /* Enable Multi Processing */ |
| 40 | gnvs->pcnt = dev_count_cpu(); |
| 41 | |
| 42 | /* Enable USB ports in S3 */ |
| 43 | gnvs->s3u0 = 1; |
| 44 | gnvs->s3u1 = 1; |
| 45 | |
| 46 | /* |
| 47 | * Enable Front USB ports in S5 by default |
| 48 | * to be consistent with back port behavior |
| 49 | */ |
| 50 | gnvs->s5u0 = 1; |
| 51 | gnvs->s5u1 = 1; |
| 52 | |
| 53 | /* IGD Displays */ |
| 54 | gnvs->ndid = 3; |
| 55 | gnvs->did[0] = 0x80000100; |
| 56 | gnvs->did[1] = 0x80000240; |
| 57 | gnvs->did[2] = 0x80000410; |
| 58 | gnvs->did[3] = 0x80000410; |
| 59 | gnvs->did[4] = 0x00000005; |
| 60 | |
| 61 | } |
| 62 | |
| 63 | unsigned long acpi_fill_madt(unsigned long current) |
| 64 | { |
| 65 | /* Local APICs */ |
| 66 | current = acpi_create_madt_lapics(current); |
| 67 | |
| 68 | /* IOAPIC */ |
| 69 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, |
| 70 | 2, IO_APIC_ADDR, 0); |
| 71 | |
| 72 | /* INT_SRC_OVR */ |
| 73 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 74 | current, 0, 0, 2, 0); |
| 75 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 76 | current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); |
| 77 | |
| 78 | return current; |
| 79 | } |