Gitiles
Code Review Sign In
review.coreboot.org / coreboot / b0b9bbc41ce335d9a60d6c7f9c9a868e0d566f8a / . / src / mainboard / google / brya / variants / anraggar / gpio.c
blob: 6eac21a7a1f714628b054c9ec1c341b4bd6b6d25 [file] [log] [blame]
wuweiminb0b9bbc2023-10-17 16:03:08 +0800[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3#include <baseboard/gpio.h>
4#include <baseboard/variants.h>
5#include <commonlib/helpers.h>
6#include <soc/gpio.h>
7
8/* Pad configuration in ramstage */
9static const struct pad_config override_gpio_table[] = {
10 /* A7 : NC ==> LTE_Present */
11 PAD_CFG_GPI(GPP_A7, NONE, DEEP),
12 /* A18 : NC ==> HDMI_HPD_SRC*/
13 PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
14
15 /* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD ==> NC */
16 PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
17 /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P ==> NC */
18 PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG),
19 /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N ==> NC */
20 PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
21
22 /* B5 : I2C2_SDA ==> SOC_I2C_SUB_SDA ==> MIPI_WCAM_SDA */
23 PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
24 /* B6 : I2C2_SCL ==> SOC_I2C_SUB_SCL ==> MIPI_WCAM_SCL */
25 PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
26
27 /* B11 : NC ==> EN_PP3300_WLAN_X*/
28 PAD_CFG_GPO(GPP_B11, 0, DEEP),
29
30 /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */
31 PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
32 /* D13 : NC ==> EN_PP1800_WCAM_X */
33 PAD_CFG_GPO_LOCK(GPP_D13, 0, LOCK_CONFIG),
34
35 /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL ==> NC */
36 PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
37 /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP ==> GPP_E21_STRAP */
38 PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
39
40 /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
41 PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
42 /* H23 : WWAN_SAR_DETECT_ODL */
43 PAD_CFG_GPO(GPP_H23, 1, DEEP),
44
45 /* F11 : NC ==> WWAN_PWR_ON */
46 PAD_CFG_GPO_LOCK(GPP_F11, 1, LOCK_CONFIG),
47 /* F12 : GSXDOUT ==> WWAN_RST_L */
48 PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
49 /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD ==> EN_PP2800_AVDD*/
50 PAD_CFG_GPO(GPP_F18, 0, DEEP),
51 /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL ==> NC*/
52 PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),
53
54
55 /* H12 : UART0_RTS# ==> SD_PERST_L ==> NC*/
56 PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
57 /* H13 : UART0_CTS# ==> EN_PP3300_SD_X ==> NC */
58 PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
59 /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
60 PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
61 /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
62 PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
63
64 /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R ==> NC */
65 PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
66 /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA ==> NC */
67 PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
68};
69
70/* Early pad configuration in bootblock */
71static const struct pad_config early_gpio_table[] = {
72 /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
73 PAD_CFG_GPO(GPP_H20, 0, DEEP),
74 /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
75 PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
76 /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
77 PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
78
79 /* F11 : NC ==> WWAN_PWR_ON */
80 PAD_CFG_GPO(GPP_F11, 1, DEEP),
81 /* F12 : GSXDOUT ==> WWAN_RST_L */
82 PAD_CFG_GPO(GPP_F12, 0, DEEP),
83 /* F16 : NC ==> WWAN_PWR_ENABLE */
84 PAD_CFG_GPO(GPP_F16, 1, DEEP),
85
86 /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
87 PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
88 /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
89 PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
90
91 /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
92 PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
93 /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
94 PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
95};
96
97static const struct pad_config romstage_gpio_table[] = {
98 /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
99 PAD_CFG_GPO(GPP_H20, 1, DEEP),
100};
101
102const struct pad_config *variant_gpio_override_table(size_t *num)
103{
104 *num = ARRAY_SIZE(override_gpio_table);
105 return override_gpio_table;
106}
107
108const struct pad_config *variant_early_gpio_table(size_t *num)
109{
110 *num = ARRAY_SIZE(early_gpio_table);
111 return early_gpio_table;
112}
113
114const struct pad_config *variant_romstage_gpio_table(size_t *num)
115{
116 *num = ARRAY_SIZE(romstage_gpio_table);
117 return romstage_gpio_table;
118}