Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/cpu.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <string.h> |
| 25 | #include <cpu/x86/msr.h> |
| 26 | #include <soc/cpu.h> |
| 27 | #include <soc/pch.h> |
| 28 | #include <soc/pci_devs.h> |
| 29 | #include <soc/romstage.h> |
| 30 | #include <soc/systemagent.h> |
| 31 | |
| 32 | static struct { |
| 33 | u32 cpuid; |
| 34 | const char *name; |
| 35 | } cpu_table[] = { |
| 36 | { CPUID_HASWELL_A0, "Haswell A0" }, |
| 37 | { CPUID_HASWELL_B0, "Haswell B0" }, |
| 38 | { CPUID_HASWELL_C0, "Haswell C0" }, |
| 39 | { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, |
| 40 | { CPUID_HASWELL_ULT, "Haswell ULT C0 or D0" }, |
| 41 | { CPUID_HASWELL_HALO, "Haswell Perf Halo" }, |
| 42 | { CPUID_BROADWELL_C0, "Broadwell C0" }, |
| 43 | { CPUID_BROADWELL_D0, "Broadwell D0" }, |
| 44 | { CPUID_BROADWELL_E0, "Broadwell E0 or F0" }, |
| 45 | }; |
| 46 | |
| 47 | static struct { |
| 48 | u8 revid; |
| 49 | const char *name; |
| 50 | } mch_rev_table[] = { |
| 51 | { MCH_BROADWELL_REV_D0, "Broadwell D0" }, |
| 52 | { MCH_BROADWELL_REV_E0, "Broadwell E0" }, |
| 53 | { MCH_BROADWELL_REV_F0, "Broadwell F0" }, |
| 54 | }; |
| 55 | |
| 56 | static struct { |
| 57 | u16 lpcid; |
| 58 | const char *name; |
| 59 | } pch_table[] = { |
| 60 | { PCH_LPT_LP_SAMPLE, "LynxPoint LP Sample" }, |
| 61 | { PCH_LPT_LP_PREMIUM, "LynxPoint LP Premium" }, |
| 62 | { PCH_LPT_LP_MAINSTREAM, "LynxPoint LP Mainstream" }, |
| 63 | { PCH_LPT_LP_VALUE, "LynxPoint LP Value" }, |
| 64 | { PCH_WPT_HSW_U_SAMPLE, "Haswell U Sample" }, |
| 65 | { PCH_WPT_BDW_U_SAMPLE, "Broadwell U Sample" }, |
| 66 | { PCH_WPT_BDW_U_PREMIUM, "Broadwell U Premium" }, |
| 67 | { PCH_WPT_BDW_U_BASE, "Broadwell U Base" }, |
| 68 | { PCH_WPT_BDW_Y_SAMPLE, "Broadwell Y Sample" }, |
| 69 | { PCH_WPT_BDW_Y_PREMIUM, "Broadwell Y Premium" }, |
| 70 | { PCH_WPT_BDW_Y_BASE, "Broadwell Y Base" }, |
| 71 | { PCH_WPT_BDW_H, "Broadwell H" }, |
| 72 | }; |
| 73 | |
| 74 | static struct { |
| 75 | u16 igdid; |
| 76 | const char *name; |
| 77 | } igd_table[] = { |
| 78 | { IGD_HASWELL_ULT_GT1, "Haswell ULT GT1" }, |
| 79 | { IGD_HASWELL_ULT_GT2, "Haswell ULT GT2" }, |
| 80 | { IGD_HASWELL_ULT_GT3, "Haswell ULT GT3" }, |
| 81 | { IGD_BROADWELL_U_GT1, "Broadwell U GT1" }, |
| 82 | { IGD_BROADWELL_U_GT2, "Broadwell U GT2" }, |
| 83 | { IGD_BROADWELL_U_GT3_15W, "Broadwell U GT3 (15W)" }, |
| 84 | { IGD_BROADWELL_U_GT3_28W, "Broadwell U GT3 (28W)" }, |
| 85 | { IGD_BROADWELL_Y_GT2, "Broadwell Y GT2" }, |
| 86 | { IGD_BROADWELL_H_GT2, "Broadwell U GT2" }, |
| 87 | { IGD_BROADWELL_H_GT3, "Broadwell U GT3" }, |
| 88 | }; |
| 89 | |
| 90 | static void report_cpu_info(void) |
| 91 | { |
| 92 | struct cpuid_result cpuidr; |
| 93 | u32 i, index; |
| 94 | char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ |
| 95 | int vt, txt, aes; |
| 96 | msr_t microcode_ver; |
| 97 | const char *mode[] = {"NOT ", ""}; |
| 98 | const char *cpu_type = "Unknown"; |
| 99 | |
| 100 | index = 0x80000000; |
| 101 | cpuidr = cpuid(index); |
| 102 | if (cpuidr.eax < 0x80000004) { |
| 103 | strcpy(cpu_string, "Platform info not available"); |
| 104 | } else { |
| 105 | u32 *p = (u32*) cpu_string; |
| 106 | for (i = 2; i <= 4 ; i++) { |
| 107 | cpuidr = cpuid(index + i); |
| 108 | *p++ = cpuidr.eax; |
| 109 | *p++ = cpuidr.ebx; |
| 110 | *p++ = cpuidr.ecx; |
| 111 | *p++ = cpuidr.edx; |
| 112 | } |
| 113 | } |
| 114 | /* Skip leading spaces in CPU name string */ |
| 115 | while (cpu_name[0] == ' ') |
| 116 | cpu_name++; |
| 117 | |
| 118 | microcode_ver.lo = 0; |
| 119 | microcode_ver.hi = 0; |
| 120 | wrmsr(0x8B, microcode_ver); |
| 121 | cpuidr = cpuid(1); |
| 122 | microcode_ver = rdmsr(0x8b); |
| 123 | |
| 124 | /* Look for string to match the name */ |
| 125 | for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { |
| 126 | if (cpu_table[i].cpuid == cpuidr.eax) { |
| 127 | cpu_type = cpu_table[i].name; |
| 128 | break; |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); |
| 133 | printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", |
| 134 | cpuidr.eax, cpu_type, microcode_ver.hi); |
| 135 | |
| 136 | aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; |
| 137 | txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; |
| 138 | vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; |
| 139 | printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, " |
| 140 | "VT %ssupported\n", mode[aes], mode[txt], mode[vt]); |
| 141 | } |
| 142 | |
| 143 | static void report_mch_info(void) |
| 144 | { |
| 145 | int i; |
| 146 | u16 mch_device = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); |
| 147 | u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); |
| 148 | const char *mch_type = "Unknown"; |
| 149 | |
| 150 | /* Look for string to match the revision for Broadwell U/Y */ |
| 151 | if (mch_device == MCH_BROADWELL_ID_U_Y) { |
| 152 | for (i = 0; i < ARRAY_SIZE(mch_rev_table); i++) { |
| 153 | if (mch_rev_table[i].revid == mch_revision) { |
| 154 | mch_type = mch_rev_table[i].name; |
| 155 | break; |
| 156 | } |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", |
| 161 | mch_device, mch_revision, mch_type); |
| 162 | } |
| 163 | |
| 164 | static void report_pch_info(void) |
| 165 | { |
| 166 | int i; |
| 167 | u16 lpcid = pch_type(); |
| 168 | const char *pch_type = "Unknown"; |
| 169 | |
| 170 | for (i = 0; i < ARRAY_SIZE(pch_table); i++) { |
| 171 | if (pch_table[i].lpcid == lpcid) { |
| 172 | pch_type = pch_table[i].name; |
| 173 | break; |
| 174 | } |
| 175 | } |
| 176 | printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", |
| 177 | lpcid, pch_revision(), pch_type); |
| 178 | } |
| 179 | |
| 180 | static void report_igd_info(void) |
| 181 | { |
| 182 | int i; |
| 183 | u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); |
| 184 | const char *igd_type = "Unknown"; |
| 185 | |
| 186 | for (i = 0; i < ARRAY_SIZE(igd_table); i++) { |
| 187 | if (igd_table[i].igdid == igdid) { |
| 188 | igd_type = igd_table[i].name; |
| 189 | break; |
| 190 | } |
| 191 | } |
| 192 | printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", |
| 193 | igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); |
| 194 | } |
| 195 | |
| 196 | void report_platform_info(void) |
| 197 | { |
| 198 | report_cpu_info(); |
| 199 | report_mch_info(); |
| 200 | report_pch_info(); |
| 201 | report_igd_info(); |
| 202 | } |
| 203 | |
| 204 | /* |
| 205 | * Dump in the log memory controller configuration as read from the memory |
| 206 | * controller registers. |
| 207 | */ |
| 208 | void report_memory_config(void) |
| 209 | { |
| 210 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 211 | int i; |
| 212 | |
| 213 | addr_decoder_common = MCHBAR32(0x5000); |
| 214 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 215 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 216 | |
| 217 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
| 218 | (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); |
| 219 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 220 | addr_decoder_common & 3, |
| 221 | (addr_decoder_common >> 2) & 3, |
| 222 | (addr_decoder_common >> 4) & 3); |
| 223 | |
| 224 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 225 | u32 ch_conf = addr_decode_ch[i]; |
| 226 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", |
| 227 | i, ch_conf); |
| 228 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 229 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 230 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 231 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
| 232 | printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", |
| 233 | ((ch_conf >> 0) & 0xff) * 256, |
| 234 | ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", |
| 235 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 236 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 237 | printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", |
| 238 | ((ch_conf >> 8) & 0xff) * 256, |
| 239 | ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", |
| 240 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 241 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 242 | } |
| 243 | } |