Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <soc/iomap.h> |
| 22 | |
| 23 | Name (_HID, EISAID ("PNP0A08")) // PCIe |
| 24 | Name (_CID, EISAID ("PNP0A03")) // PCI |
| 25 | |
| 26 | Name (_ADR, 0) |
| 27 | Name (_BBN, 0) |
| 28 | |
| 29 | Device (MCHC) |
| 30 | { |
| 31 | Name (_ADR, 0x00000000) // 0:0.0 |
| 32 | |
| 33 | OperationRegion (MCHP, PCI_Config, 0x00, 0x100) |
| 34 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 35 | { |
| 36 | Offset (0x70), // ME Base Address |
| 37 | MEBA, 64, |
| 38 | Offset (0xa0), // Top of Used Memory |
| 39 | TOM, 64, |
| 40 | Offset (0xbc), // Top of Low Used Memory |
| 41 | TLUD, 32, |
| 42 | } |
| 43 | } |
| 44 | |
| 45 | // Current Resource Settings |
| 46 | |
| 47 | Method (_CRS, 0, Serialized) |
| 48 | { |
| 49 | Name (MCRS, ResourceTemplate() |
| 50 | { |
| 51 | // Bus Numbers |
| 52 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 53 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 54 | |
| 55 | // IO Region 0 |
| 56 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 57 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 58 | |
| 59 | // PCI Config Space |
| 60 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 61 | |
| 62 | // IO Region 1 |
| 63 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 64 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 65 | |
| 66 | // VGA memory (0xa0000-0xbffff) |
| 67 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 68 | Cacheable, ReadWrite, |
| 69 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 70 | 0x00020000,,, ASEG) |
| 71 | |
| 72 | // OPROM reserved (0xc0000-0xc3fff) |
| 73 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 74 | Cacheable, ReadWrite, |
| 75 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 76 | 0x00004000,,, OPR0) |
| 77 | |
| 78 | // OPROM reserved (0xc4000-0xc7fff) |
| 79 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 80 | Cacheable, ReadWrite, |
| 81 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 82 | 0x00004000,,, OPR1) |
| 83 | |
| 84 | // OPROM reserved (0xc8000-0xcbfff) |
| 85 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 86 | Cacheable, ReadWrite, |
| 87 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 88 | 0x00004000,,, OPR2) |
| 89 | |
| 90 | // OPROM reserved (0xcc000-0xcffff) |
| 91 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 92 | Cacheable, ReadWrite, |
| 93 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 94 | 0x00004000,,, OPR3) |
| 95 | |
| 96 | // OPROM reserved (0xd0000-0xd3fff) |
| 97 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 98 | Cacheable, ReadWrite, |
| 99 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 100 | 0x00004000,,, OPR4) |
| 101 | |
| 102 | // OPROM reserved (0xd4000-0xd7fff) |
| 103 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 104 | Cacheable, ReadWrite, |
| 105 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 106 | 0x00004000,,, OPR5) |
| 107 | |
| 108 | // OPROM reserved (0xd8000-0xdbfff) |
| 109 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 110 | Cacheable, ReadWrite, |
| 111 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 112 | 0x00004000,,, OPR6) |
| 113 | |
| 114 | // OPROM reserved (0xdc000-0xdffff) |
| 115 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 116 | Cacheable, ReadWrite, |
| 117 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 118 | 0x00004000,,, OPR7) |
| 119 | |
| 120 | // BIOS Extension (0xe0000-0xe3fff) |
| 121 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 122 | Cacheable, ReadWrite, |
| 123 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 124 | 0x00004000,,, ESG0) |
| 125 | |
| 126 | // BIOS Extension (0xe4000-0xe7fff) |
| 127 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 128 | Cacheable, ReadWrite, |
| 129 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 130 | 0x00004000,,, ESG1) |
| 131 | |
| 132 | // BIOS Extension (0xe8000-0xebfff) |
| 133 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 134 | Cacheable, ReadWrite, |
| 135 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 136 | 0x00004000,,, ESG2) |
| 137 | |
| 138 | // BIOS Extension (0xec000-0xeffff) |
| 139 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 140 | Cacheable, ReadWrite, |
| 141 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 142 | 0x00004000,,, ESG3) |
| 143 | |
| 144 | // System BIOS (0xf0000-0xfffff) |
| 145 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 146 | Cacheable, ReadWrite, |
| 147 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 148 | 0x00010000,,, FSEG) |
| 149 | |
| 150 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
| 151 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 152 | Cacheable, ReadWrite, |
| 153 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 154 | 0x00000000,,, PM01) |
| 155 | |
| 156 | // TPM Area (0xfed40000-0xfed44fff) |
| 157 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 158 | Cacheable, ReadWrite, |
| 159 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 160 | 0x00005000,,, TPMR) |
| 161 | }) |
| 162 | |
| 163 | // Find PCI resource area in MCRS |
| 164 | CreateDwordField(MCRS, PM01._MIN, PMIN) |
| 165 | CreateDwordField(MCRS, PM01._MAX, PMAX) |
| 166 | CreateDwordField(MCRS, PM01._LEN, PLEN) |
| 167 | |
| 168 | // Fix up PCI memory region |
| 169 | // Start with Top of Lower Usable DRAM |
| 170 | Store (^MCHC.TLUD, Local0) |
| 171 | Store (^MCHC.MEBA, Local1) |
| 172 | |
| 173 | // Check if ME base is equal |
| 174 | If (LEqual (Local0, Local1)) { |
| 175 | // Use Top Of Memory instead |
| 176 | Store (^MCHC.TOM, Local0) |
| 177 | } |
| 178 | |
| 179 | Store (Local0, PMIN) |
| 180 | Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) |
| 181 | Add(Subtract(PMAX, PMIN), 1, PLEN) |
| 182 | |
| 183 | Return (MCRS) |
| 184 | } |
| 185 | |
| 186 | /* PCI Device Resource Consumption */ |
| 187 | Device (PDRC) |
| 188 | { |
| 189 | Name (_HID, EISAID("PNP0C02")) |
| 190 | Name (_UID, 1) |
| 191 | |
| 192 | Name (PDRS, ResourceTemplate() { |
| 193 | Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) |
| 194 | Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE) |
| 195 | Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE) |
| 196 | Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE) |
| 197 | Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) |
| 198 | Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE) |
| 199 | Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE) |
| 200 | }) |
| 201 | |
| 202 | // Current Resource Settings |
| 203 | Method (_CRS, 0, Serialized) |
| 204 | { |
| 205 | Return (PDRS) |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | /* PCI IRQ assignment */ |
| 210 | #include "pci_irqs.asl" |
| 211 | |
| 212 | /* Configurable TDP */ |
| 213 | #include "ctdp.asl" |