Duncan Laurie | afad056 | 2013-01-14 08:50:03 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <arch/romcc_io.h> |
| 27 | #include <device/pci_def.h> |
| 28 | #include <device/pnp_def.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include <pc80/mc146818rtc.h> |
| 31 | #include <cbmem.h> |
| 32 | #include <console/console.h> |
| 33 | #include "northbridge/intel/haswell/haswell.h" |
| 34 | #include "northbridge/intel/haswell/raminit.h" |
| 35 | #include "southbridge/intel/lynxpoint/me.h" |
| 36 | #include "southbridge/intel/lynxpoint/pch.h" |
| 37 | #include "southbridge/intel/lynxpoint/lp_gpio.h" |
| 38 | #include <arch/cpu.h> |
| 39 | #include <cpu/x86/bist.h> |
| 40 | #include <cpu/x86/msr.h> |
| 41 | #include "gpio.h" |
| 42 | #if CONFIG_CHROMEOS |
| 43 | #include <vendorcode/google/chromeos/chromeos.h> |
| 44 | #endif |
| 45 | |
| 46 | const struct rcba_config_instruction rcba_config[] = { |
| 47 | |
| 48 | /* |
| 49 | * GFX INTA -> PIRQA (MSI) |
| 50 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 51 | * D28IP_P4IP ETH0 INTB -> PIRQC |
| 52 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 53 | * D20IP_XHCI XHCI INTA -> PIRQA |
| 54 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 55 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 56 | * D31IP_TTIP THRT INTC -> PIRQH |
| 57 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 58 | */ |
| 59 | |
| 60 | /* Device interrupt pin register (board specific) */ |
| 61 | RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 62 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), |
| 63 | RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), |
| 64 | RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 65 | (INTB << D28IP_P4IP)), |
| 66 | RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), |
| 67 | RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), |
| 68 | RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), |
| 69 | RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), |
| 70 | RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)), |
| 71 | |
| 72 | /* Device interrupt route registers */ |
| 73 | RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), |
| 74 | RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), |
| 75 | RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), |
| 76 | RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), |
| 77 | RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), |
| 78 | RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
| 79 | RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
| 80 | RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
| 81 | RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), |
| 82 | RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)), |
| 83 | |
| 84 | /* Disable unused devices (board specific) */ |
| 85 | RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), |
| 86 | |
| 87 | RCBA_END_CONFIG, |
| 88 | }; |
| 89 | |
| 90 | void main(unsigned long bist) |
| 91 | { |
| 92 | int boot_mode = 0; |
| 93 | int wake_from_s3; |
| 94 | int cbmem_was_initted; |
| 95 | |
| 96 | #if CONFIG_COLLECT_TIMESTAMPS |
| 97 | tsc_t start_romstage_time; |
| 98 | tsc_t before_dram_time; |
| 99 | tsc_t after_dram_time; |
| 100 | tsc_t base_time = { |
| 101 | .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), |
| 102 | .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) |
| 103 | }; |
| 104 | #endif |
| 105 | struct pei_data pei_data = { |
| 106 | pei_version: PEI_VERSION, |
| 107 | mchbar: DEFAULT_MCHBAR, |
| 108 | dmibar: DEFAULT_DMIBAR, |
| 109 | epbar: DEFAULT_EPBAR, |
| 110 | pciexbar: DEFAULT_PCIEXBAR, |
| 111 | smbusbar: SMBUS_IO_BASE, |
| 112 | wdbbar: 0x4000000, |
| 113 | wdbsize: 0x1000, |
| 114 | hpet_address: HPET_ADDR, |
| 115 | rcba: DEFAULT_RCBA, |
| 116 | pmbase: DEFAULT_PMBASE, |
| 117 | gpiobase: DEFAULT_GPIOBASE, |
| 118 | temp_mmio_base: 0xfed08000, |
| 119 | system_type: 5, /* ULT */ |
| 120 | tseg_size: CONFIG_SMM_TSEG_SIZE, |
| 121 | spd_addresses: { 0xa2, 0x00, 0xa2, 0x00 }, |
| 122 | ec_present: 1, |
| 123 | // 0 = leave channel enabled |
| 124 | // 1 = disable dimm 0 on channel |
| 125 | // 2 = disable dimm 1 on channel |
| 126 | // 3 = disable dimm 0+1 on channel |
| 127 | dimm_channel0_disabled: 2, |
| 128 | dimm_channel1_disabled: 2, |
| 129 | max_ddr3_freq: 1600, |
| 130 | usb_port_config: { |
| 131 | { 1, 0, 0x0040 }, /* P0: */ |
| 132 | { 1, 0, 0x0040 }, /* P1: */ |
| 133 | { 1, 0, 0x0040 }, /* P2: */ |
| 134 | { 1, 0, 0x0040 }, /* P3: */ |
| 135 | { 1, 0, 0x0040 }, /* P4: */ |
| 136 | { 1, 0, 0x0040 }, /* P5: */ |
| 137 | { 1, 0, 0x0040 }, /* P6: */ |
| 138 | { 1, 0, 0x0040 }, /* P7: */ |
| 139 | { 1, 0, 0x0040 }, /* P8: */ |
| 140 | { 1, 0, 0x0040 }, /* P9: */ |
| 141 | { 1, 0, 0x0040 }, /* P10: */ |
| 142 | { 1, 0, 0x0000 }, /* P11: */ |
| 143 | { 1, 0, 0x0040 }, /* P12: */ |
| 144 | { 1, 0, 0x0040 }, /* P13: */ |
| 145 | }, |
| 146 | }; |
| 147 | |
| 148 | #if CONFIG_COLLECT_TIMESTAMPS |
| 149 | start_romstage_time = rdtsc(); |
| 150 | #endif |
| 151 | |
| 152 | if (bist == 0) |
| 153 | enable_lapic(); |
| 154 | |
| 155 | wake_from_s3 = early_pch_init(&mainboard_gpio_map, &rcba_config[0]); |
| 156 | |
| 157 | /* Halt if there was a built in self test failure */ |
| 158 | report_bist_failure(bist); |
| 159 | |
| 160 | /* Perform some early chipset initialization required |
| 161 | * before RAM initialization can work |
| 162 | */ |
| 163 | haswell_early_initialization(HASWELL_MOBILE); |
| 164 | printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); |
| 165 | |
| 166 | if (wake_from_s3) { |
| 167 | #if CONFIG_HAVE_ACPI_RESUME |
| 168 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
| 169 | boot_mode = 2; |
| 170 | #else |
| 171 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
| 172 | #endif |
| 173 | } |
| 174 | |
| 175 | /* Prepare USB controller early in S3 resume */ |
| 176 | if (boot_mode == 2) |
| 177 | enable_usb_bar(); |
| 178 | |
| 179 | post_code(0x3a); |
| 180 | pei_data.boot_mode = boot_mode; |
| 181 | #if CONFIG_COLLECT_TIMESTAMPS |
| 182 | before_dram_time = rdtsc(); |
| 183 | #endif |
| 184 | |
| 185 | report_platform_info(); |
| 186 | |
| 187 | sdram_initialize(&pei_data); |
| 188 | |
| 189 | #if CONFIG_COLLECT_TIMESTAMPS |
| 190 | after_dram_time = rdtsc(); |
| 191 | #endif |
| 192 | post_code(0x3b); |
| 193 | |
| 194 | intel_early_me_status(); |
| 195 | |
| 196 | quick_ram_check(); |
| 197 | post_code(0x3e); |
| 198 | |
| 199 | MCHBAR16(SSKPD) = 0xCAFE; |
| 200 | #if CONFIG_EARLY_CBMEM_INIT |
| 201 | cbmem_was_initted = !cbmem_initialize(); |
| 202 | #else |
| 203 | cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() |
| 204 | - HIGH_MEMORY_SIZE)); |
| 205 | #endif |
| 206 | |
| 207 | #if CONFIG_HAVE_ACPI_RESUME |
| 208 | /* If there is no high memory area, we didn't boot before, so |
| 209 | * this is not a resume. In that case we just create the cbmem toc. |
| 210 | */ |
| 211 | |
| 212 | *(u32 *)CBMEM_BOOT_MODE = 0; |
| 213 | *(u32 *)CBMEM_RESUME_BACKUP = 0; |
| 214 | |
| 215 | if ((boot_mode == 2) && cbmem_was_initted) { |
| 216 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 217 | if (resume_backup_memory) { |
| 218 | *(u32 *)CBMEM_BOOT_MODE = boot_mode; |
| 219 | *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; |
| 220 | } |
| 221 | /* Magic for S3 resume */ |
| 222 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 223 | } else if (boot_mode == 2) { |
| 224 | /* Failed S3 resume, reset to come up cleanly */ |
| 225 | outb(0x6, 0xcf9); |
| 226 | while (1) { |
| 227 | hlt(); |
| 228 | } |
| 229 | } else { |
| 230 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
| 231 | } |
| 232 | #endif |
| 233 | post_code(0x3f); |
| 234 | #if CONFIG_CHROMEOS |
| 235 | init_chromeos(boot_mode); |
| 236 | #endif |
| 237 | #if CONFIG_COLLECT_TIMESTAMPS |
| 238 | timestamp_init(base_time); |
| 239 | timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); |
| 240 | timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); |
| 241 | timestamp_add(TS_AFTER_INITRAM, after_dram_time ); |
| 242 | timestamp_add_now(TS_END_ROMSTAGE); |
| 243 | #endif |
| 244 | #if CONFIG_CONSOLE_CBMEM |
| 245 | /* Keep this the last thing this function does. */ |
| 246 | cbmemc_reinit(); |
| 247 | #endif |
| 248 | } |