blob: 18c9bb25d5a57b26d630f456ea98cfff8a31b6ba [file] [log] [blame]
Duncan Laurieafad0562013-01-14 08:50:03 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <types.h>
21#include <string.h>
22#include <cbmem.h>
23#include <console/console.h>
24#include <arch/acpi.h>
25#include <arch/ioapic.h>
26#include <arch/acpigen.h>
27#include <arch/smp/mpspec.h>
28#include <device/device.h>
29#include <device/pci.h>
30#include <device/pci_ids.h>
31#include <cpu/cpu.h>
32#include <cpu/x86/msr.h>
33#include <vendorcode/google/chromeos/gnvs.h>
34
35extern const unsigned char AmlCode[];
36#if CONFIG_HAVE_ACPI_SLIC
37unsigned long acpi_create_slic(unsigned long current);
38#endif
39
40#include <southbridge/intel/lynxpoint/pch.h>
41#include <southbridge/intel/lynxpoint/nvs.h>
42#include "thermal.h"
43
44static void acpi_update_thermal_table(global_nvs_t *gnvs)
45{
46 gnvs->f4of = FAN4_THRESHOLD_OFF;
47 gnvs->f4on = FAN4_THRESHOLD_ON;
48 gnvs->f4pw = FAN4_PWM;
49
50 gnvs->f3of = FAN3_THRESHOLD_OFF;
51 gnvs->f3on = FAN3_THRESHOLD_ON;
52 gnvs->f3pw = FAN3_PWM;
53
54 gnvs->f2of = FAN2_THRESHOLD_OFF;
55 gnvs->f2on = FAN2_THRESHOLD_ON;
56 gnvs->f2pw = FAN2_PWM;
57
58 gnvs->f1of = FAN1_THRESHOLD_OFF;
59 gnvs->f1on = FAN1_THRESHOLD_ON;
60 gnvs->f1pw = FAN1_PWM;
61
62 gnvs->f0of = FAN0_THRESHOLD_OFF;
63 gnvs->f0on = FAN0_THRESHOLD_ON;
64 gnvs->f0pw = FAN0_PWM;
65
66 gnvs->tcrt = CRITICAL_TEMPERATURE;
67 gnvs->tpsv = PASSIVE_TEMPERATURE;
68 gnvs->tmax = MAX_TEMPERATURE;
69}
70
71static void acpi_create_gnvs(global_nvs_t *gnvs)
72{
73 memset((void *)gnvs, 0, sizeof(*gnvs));
74 gnvs->apic = 1;
75 gnvs->mpen = 1; /* Enable Multi Processing */
76 gnvs->pcnt = dev_count_cpu();
77
78 /* Enable USB ports in S3 */
79 gnvs->s3u0 = 1;
80 gnvs->s3u1 = 1;
81
82 /* Disable USB ports in S5 */
83 gnvs->s5u0 = 0;
84 gnvs->s5u1 = 0;
85
86 /* CBMEM TOC */
87 gnvs->cmem = (u32)get_cbmem_toc();
88
89 /* IGD Displays */
90 gnvs->ndid = 3;
91 gnvs->did[0] = 0x80000100;
92 gnvs->did[1] = 0x80000240;
93 gnvs->did[2] = 0x80000410;
94 gnvs->did[3] = 0x80000410;
95 gnvs->did[4] = 0x00000005;
96
97#if CONFIG_CHROMEOS
98 // TODO(reinauer) this could move elsewhere?
99 chromeos_init_vboot(&(gnvs->chromeos));
100 /* Emerald Lake has no EC (?) */
101 gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
102#endif
103
104 acpi_update_thermal_table(gnvs);
105}
106
107unsigned long acpi_fill_madt(unsigned long current)
108{
109 /* Local APICs */
110 current = acpi_create_madt_lapics(current);
111
112 /* IOAPIC */
113 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
114 2, IO_APIC_ADDR, 0);
115
116 /* INT_SRC_OVR */
117 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
118 current, 0, 0, 2, 0);
119 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
120 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
121
122 return current;
123}
124
125unsigned long acpi_fill_ssdt_generator(unsigned long current,
126 const char *oem_table_id)
127{
128 generate_cpu_entries();
129 return (unsigned long) (acpigen_get_current());
130}
131
132unsigned long acpi_fill_slit(unsigned long current)
133{
134 // Not implemented
135 return current;
136}
137
138unsigned long acpi_fill_srat(unsigned long current)
139{
140 /* No NUMA, no SRAT */
141 return current;
142}
143
144#define ALIGN_CURRENT current = (ALIGN(current, 16))
145unsigned long write_acpi_tables(unsigned long start)
146{
147 unsigned long current;
148 int i;
149 acpi_rsdp_t *rsdp;
150 acpi_rsdt_t *rsdt;
151 acpi_xsdt_t *xsdt;
152 acpi_hpet_t *hpet;
153 acpi_madt_t *madt;
154 acpi_mcfg_t *mcfg;
155 acpi_fadt_t *fadt;
156 acpi_facs_t *facs;
157#if CONFIG_HAVE_ACPI_SLIC
158 acpi_header_t *slic;
159#endif
160 acpi_header_t *ssdt;
161 acpi_header_t *dsdt;
162
163 current = start;
164
165 /* Align ACPI tables to 16byte */
166 ALIGN_CURRENT;
167
168 printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
169
170 /* We need at least an RSDP and an RSDT Table */
171 rsdp = (acpi_rsdp_t *) current;
172 current += sizeof(acpi_rsdp_t);
173 ALIGN_CURRENT;
174 rsdt = (acpi_rsdt_t *) current;
175 current += sizeof(acpi_rsdt_t);
176 ALIGN_CURRENT;
177 xsdt = (acpi_xsdt_t *) current;
178 current += sizeof(acpi_xsdt_t);
179 ALIGN_CURRENT;
180
181 /* clear all table memory */
182 memset((void *) start, 0, current - start);
183
184 acpi_write_rsdp(rsdp, rsdt, xsdt);
185 acpi_write_rsdt(rsdt);
186 acpi_write_xsdt(xsdt);
187
188 printk(BIOS_DEBUG, "ACPI: * FACS\n");
189 facs = (acpi_facs_t *) current;
190 current += sizeof(acpi_facs_t);
191 ALIGN_CURRENT;
192 acpi_create_facs(facs);
193
194 printk(BIOS_DEBUG, "ACPI: * DSDT\n");
195 dsdt = (acpi_header_t *) current;
196 memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
197 current += dsdt->length;
198 memcpy(dsdt, &AmlCode, dsdt->length);
199
200 ALIGN_CURRENT;
201
202 printk(BIOS_DEBUG, "ACPI: * FADT\n");
203 fadt = (acpi_fadt_t *) current;
204 current += sizeof(acpi_fadt_t);
205 ALIGN_CURRENT;
206
207 acpi_create_fadt(fadt, facs, dsdt);
208 acpi_add_table(rsdp, fadt);
209
210 /*
211 * We explicitly add these tables later on:
212 */
213 printk(BIOS_DEBUG, "ACPI: * HPET\n");
214
215 hpet = (acpi_hpet_t *) current;
216 current += sizeof(acpi_hpet_t);
217 ALIGN_CURRENT;
218 acpi_create_intel_hpet(hpet);
219 acpi_add_table(rsdp, hpet);
220
221 /* If we want to use HPET Timers Linux wants an MADT */
222 printk(BIOS_DEBUG, "ACPI: * MADT\n");
223
224 madt = (acpi_madt_t *) current;
225 acpi_create_madt(madt);
226 current += madt->header.length;
227 ALIGN_CURRENT;
228 acpi_add_table(rsdp, madt);
229
230 printk(BIOS_DEBUG, "ACPI: * MCFG\n");
231 mcfg = (acpi_mcfg_t *) current;
232 acpi_create_mcfg(mcfg);
233 current += mcfg->header.length;
234 ALIGN_CURRENT;
235 acpi_add_table(rsdp, mcfg);
236
237 /* Pack GNVS into the ACPI table area */
238 for (i=0; i < dsdt->length; i++) {
239 if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
240 printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
241 "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
242 *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
243 acpi_save_gnvs(current);
244 break;
245 }
246 }
247
248 /* And fill it */
249 acpi_create_gnvs((global_nvs_t *)current);
250
251 /* And tell SMI about it */
252 smm_setup_structures((void *)current, NULL, NULL);
253
254 current += sizeof(global_nvs_t);
255 ALIGN_CURRENT;
256
257 /* We patched up the DSDT, so we need to recalculate the checksum */
258 dsdt->checksum = 0;
259 dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
260
261 printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
262 dsdt->length);
263
264#if CONFIG_HAVE_ACPI_SLIC
265 printk(BIOS_DEBUG, "ACPI: * SLIC\n");
266 slic = (acpi_header_t *)current;
267 current += acpi_create_slic(current);
268 ALIGN_CURRENT;
269 acpi_add_table(rsdp, slic);
270#endif
271
272 printk(BIOS_DEBUG, "ACPI: * SSDT\n");
273 ssdt = (acpi_header_t *)current;
274 acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
275 current += ssdt->length;
276 acpi_add_table(rsdp, ssdt);
277 ALIGN_CURRENT;
278
279 printk(BIOS_DEBUG, "current = %lx\n", current);
280 printk(BIOS_INFO, "ACPI: done.\n");
281 return current;
282}