Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 1 | chip northbridge/intel/sandybridge |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 2 | # IGD Displays |
Nico Huber | b0b25c8 | 2020-03-21 20:35:12 +0100 | [diff] [blame] | 3 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 4 | |
| 5 | # Enable DisplayPort B Hotplug with 6ms pulse |
| 6 | register "gpu_dp_b_hotplug" = "0x06" |
| 7 | |
Arthur Heymans | 8bb2ed8 | 2018-07-18 16:37:00 +0200 | [diff] [blame] | 8 | # Enable Panel as LVDS and configure power delays |
Angel Pons | dc0c081 | 2020-09-02 19:17:30 +0200 | [diff] [blame] | 9 | register "gpu_panel_port_select" = "PANEL_PORT_LVDS" |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 10 | register "gpu_panel_power_cycle_delay" = "5" # 400ms |
| 11 | register "gpu_panel_power_up_delay" = "500" # 50ms |
| 12 | register "gpu_panel_power_down_delay" = "150" # 15ms |
| 13 | register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms |
| 14 | register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms |
| 15 | |
| 16 | # Set backlight PWM values |
| 17 | register "gpu_cpu_backlight" = "0x000001d4" |
| 18 | register "gpu_pch_backlight" = "0x03aa0000" |
| 19 | |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 20 | register "max_mem_clock_mhz" = "666" |
| 21 | |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 22 | device cpu_cluster 0 on |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 23 | chip cpu/intel/model_206ax |
| 24 | # Magic APIC ID to locate this chip |
Angel Pons | c56c723 | 2021-05-17 11:03:55 +0200 | [diff] [blame] | 25 | device lapic 0 on end |
Arthur Heymans | b3f2323 | 2019-01-21 17:48:55 +0100 | [diff] [blame] | 26 | device lapic 0xacac off end |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 27 | |
Angel Pons | 6f56a23 | 2021-01-04 17:02:23 +0100 | [diff] [blame] | 28 | register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) |
| 29 | register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) |
| 30 | register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 31 | end |
| 32 | end |
| 33 | |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 34 | device domain 0 on |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 35 | device pci 00.0 on end # host bridge |
| 36 | device pci 02.0 on end # vga controller |
| 37 | |
| 38 | chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 39 | # GPI routing |
| 40 | # 0 No effect (default) |
| 41 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 42 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 43 | # Set Lid Switch to SMI to capture in recovery mode. It gets reset to |
| 44 | # SCI mode when we go to ACPI mode. |
| 45 | register "alt_gp_smi_en" = "0x8100" |
| 46 | register "gpi7_routing" = "2" |
| 47 | register "gpi8_routing" = "1" |
| 48 | register "gpi15_routing" = "1" #lid switch gpe |
| 49 | |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 50 | register "sata_port_map" = "0x1" |
| 51 | |
| 52 | # EC range is 0xFD60 (EC_IO) and 0x68/0x6C |
| 53 | register "gen1_dec" = "0x0004fd61" |
| 54 | register "gen2_dec" = "0x00040069" |
| 55 | |
| 56 | # Enable zero-based linear PCIe root port functions |
Angel Pons | af4bd56 | 2021-12-28 13:05:56 +0100 | [diff] [blame^] | 57 | register "pcie_port_coalesce" = "true" |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 58 | |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 59 | device pci 16.0 on end # Management Engine Interface 1 |
| 60 | device pci 16.1 off end # Management Engine Interface 2 |
| 61 | device pci 16.2 off end # Management Engine IDE-R |
| 62 | device pci 16.3 off end # Management Engine KT |
| 63 | device pci 19.0 off end # Intel Gigabit Ethernet |
| 64 | device pci 1a.0 on end # USB2 EHCI #2 |
| 65 | device pci 1b.0 on end # High Definition Audio |
| 66 | device pci 1c.0 off end # PCIe Port #1 |
| 67 | device pci 1c.1 on end # PCIe Port #2 (WLAN) |
| 68 | device pci 1c.2 on end # PCIe Port #3 (ETH0) |
| 69 | device pci 1c.3 off end # PCIe Port #4 |
| 70 | device pci 1c.4 off end # PCIe Port #5 |
| 71 | device pci 1c.5 off end # PCIe Port #6 |
| 72 | device pci 1c.6 off end # PCIe Port #7 |
| 73 | device pci 1c.7 off end # PCIe Port #8 |
| 74 | device pci 1d.0 on end # USB2 EHCI #1 |
| 75 | device pci 1e.0 off end # PCI bridge |
| 76 | device pci 1f.0 on |
| 77 | chip ec/compal/ene932 |
| 78 | # 60/64 KBC |
| 79 | device pnp ff.1 on # dummy address |
| 80 | end |
| 81 | end |
| 82 | end # LPC bridge |
| 83 | device pci 1f.2 on end # SATA Controller 1 |
| 84 | device pci 1f.3 on end # SMBus |
| 85 | device pci 1f.5 off end # SATA Controller 2 |
| 86 | device pci 1f.6 on end # Thermal |
| 87 | end |
| 88 | end |
| 89 | end |