blob: 8ef5ed2574011d5a3bcc86f28e456ef870035e51 [file] [log] [blame]
David Wue7f44932021-08-17 20:05:51 +08001fw_config
2 field KB_BL 0 0
3 option KB_BL_ABSENT 0
4 option KB_BL_PRESENT 1
5 end
6 field AUDIO 1 3
7 option AUDIO_UNKNOWN 0
8 option MAX98373_NAU88L25B_I2S 1
9 end
David Wueea22f62021-10-26 19:13:54 +080010 field UFC 4 5
11 option UFC_USB 0
12 option UFC_MIPI_OVTI2740 1
David Wucedd4d12022-12-16 20:53:49 +080013 option UFC_MIPI_ZYDRON 2
David Wueea22f62021-10-26 19:13:54 +080014 end
David Wua5b6ec02021-12-27 13:50:27 +080015 field STYLUS 6
16 option STYLUS_ABSENT 0
17 option STYLUS_PRESENT 1
18 end
David Wucedd4d12022-12-16 20:53:49 +080019 field ZYDRON_UFC 36 37
David Wua883c952023-01-03 12:45:05 +080020 option UFC_MIPI_OVTI2740 0
21 option UFC_MIPI_HI556 1
David Wucedd4d12022-12-16 20:53:49 +080022 end
David Wue7f44932021-08-17 20:05:51 +080023end
David Wu07375cb2021-07-08 10:58:00 +080024chip soc/intel/alderlake
David Wua1b9f052022-12-25 23:42:58 +080025 register "domain_vr_config[VR_DOMAIN_IA]" = "{
26 .enable_fast_vmode = 1,
27 }"
28
MAULIK V VAGHELA215a97e2022-03-07 18:39:17 +053029 register "sagv" = "SaGv_Enabled"
David Wu7f7424c2021-09-23 19:29:47 +080030
David Wuc6d0a4c2022-06-13 17:34:33 +080031 # As per Intel Advisory doc#723158, the change is required to prevent possible
32 # display flickering issue.
33 register "usb2_phy_sus_pg_disable" = "1"
34
David Wu6db243a2021-11-09 12:36:43 +080035 # GPE configuration
36 register "pmc_gpe0_dw1" = "GPP_D"
37
David Wu7dd92952022-04-13 16:43:54 +080038 # Acoustic settings
39 register "acoustic_noise_mitigation" = "1"
40 register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
41 register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
42 register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
43 register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
44
David Wubfc4d8e2021-11-10 12:26:22 +080045 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
46 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
David Wubfc4d8e2021-11-10 12:26:22 +080047
48 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
49
David Wu008c2b12021-10-25 15:22:21 +080050 # FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn
51 # bypass rails implemented.
52 register "ext_fivr_settings" = "{
53 .configure_ext_fivr = 1,
54 }"
55
David Wue7f44932021-08-17 20:05:51 +080056 # Intel Common SoC Config
57 #+-------------------+---------------------------+
58 #| Field | Value |
59 #+-------------------+---------------------------+
60 #| GSPI1 | Fingerprint MCU |
61 #| I2C0 | Audio |
David Wu02cef7a2021-11-23 11:26:44 +080062 #| I2C1 | cr50 TPM. Early init is |
David Wue7f44932021-08-17 20:05:51 +080063 #| | required to set up a BAR |
64 #| | for TPM communication |
David Wu02cef7a2021-11-23 11:26:44 +080065 #| I2C2 | SAR0 |
66 #| I2C3 | Touchscreen |
David Wue7f44932021-08-17 20:05:51 +080067 #| I2C5 | Trackpad |
68 #+-------------------+---------------------------+
David Wu07375cb2021-07-08 10:58:00 +080069
David Wu02cef7a2021-11-23 11:26:44 +080070 register "common_soc_config" = "{
71 .i2c[1] = {
72 .early_init = 1,
73 .speed = I2C_SPEED_FAST,
74 .rise_time_ns = 600,
75 .fall_time_ns = 400,
76 .data_hold_time_ns = 50,
77 },
78 .i2c[3] = {
David Wuad2e4ea2022-03-29 14:35:03 +080079 .speed = I2C_SPEED_FAST,
David Wu02cef7a2021-11-23 11:26:44 +080080 .rise_time_ns = 650,
81 .fall_time_ns = 400,
82 .data_hold_time_ns = 50,
83 },
84 }"
85
Patrick Rudolphf7f7b3b2023-03-29 15:34:07 +020086 register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
David Wu6555c4c2022-03-01 13:59:20 +080087 .tdp_pl1_override = 20,
88 .tdp_pl2_override = 43,
89 .tdp_pl4 = 105,
90 }"
91
92 register "power_limits_config[ADL_P_682_28W_CORE]" = "{
93 .tdp_pl1_override = 20,
94 .tdp_pl2_override = 43,
95 .tdp_pl4 = 105,
96 }"
97
Subrata Banik3d469fa2021-09-10 00:21:23 +053098 device domain 0 on
Won Chungaf1782c2023-07-31 22:27:51 +000099 device ref igpu on
100 chip drivers/gfx/generic
101 register "device_count" = "6"
102 # DDIA for eDP
103 register "device[0].name" = ""LCD""
104 # DDIB for HDMI
105 register "device[1].name" = ""DD01""
106 # TCP0 (DP-1) for port C0
107 register "device[2].name" = ""DD02""
108 register "device[2].use_pld" = "true"
109 register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
110 # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
111 register "device[3].name" = ""DD03""
112 # TCP2 (DP-3) for port C1
113 register "device[4].name" = ""DD04""
114 register "device[4].use_pld" = "true"
115 register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
116 # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
117 register "device[5].name" = ""DD05""
118 device generic 0 on end
119 end
120 end # Integrated Graphics Device
David Wue7f44932021-08-17 20:05:51 +0800121 device ref dtt on
122 chip drivers/intel/dptf
123 ## sensor information
124 register "options.tsr[0].desc" = ""DRAM""
David Wu53075c72021-11-10 14:26:27 +0800125 register "options.tsr[1].desc" = ""Soc""
126 register "options.tsr[2].desc" = ""Charger""
David Wu07375cb2021-07-08 10:58:00 +0800127
David Wue7f44932021-08-17 20:05:51 +0800128 # TODO: below values are initial reference values only
129 ## Active Policy
130 register "policies.active" = "{
131 [0] = {
132 .target = DPTF_CPU,
133 .thresholds = {
134 TEMP_PCT(85, 90),
David Wu3e8ca372021-11-23 17:04:59 +0800135 TEMP_PCT(75, 80),
136 TEMP_PCT(68, 70),
137 TEMP_PCT(62, 60),
138 TEMP_PCT(55, 50),
139 TEMP_PCT(50, 40),
140 TEMP_PCT(40, 30),
141 }
142 },
143 [1] = {
144 .target = DPTF_TEMP_SENSOR_1,
145 .thresholds = {
146 TEMP_PCT(60, 90),
147 TEMP_PCT(55, 80),
148 TEMP_PCT(52, 70),
149 TEMP_PCT(48, 60),
150 TEMP_PCT(44, 50),
151 TEMP_PCT(40, 40),
152 TEMP_PCT(36, 30),
David Wue7f44932021-08-17 20:05:51 +0800153 }
154 }
155 }"
156
157 ## Passive Policy
158 register "policies.passive" = "{
David Wu3e8ca372021-11-23 17:04:59 +0800159 [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
160 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000),
161 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000),
162 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000),
David Wue7f44932021-08-17 20:05:51 +0800163 }"
164
165 ## Critical Policy
166 register "policies.critical" = "{
David Wu3e8ca372021-11-23 17:04:59 +0800167 [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
David Wue7f44932021-08-17 20:05:51 +0800168 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
169 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
David Wu53075c72021-11-10 14:26:27 +0800170 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
David Wue7f44932021-08-17 20:05:51 +0800171 }"
172
173 register "controls.power_limits" = "{
174 .pl1 = {
David Wu3e8ca372021-11-23 17:04:59 +0800175 .min_power = 18000,
David Wu6555c4c2022-03-01 13:59:20 +0800176 .max_power = 20000,
David Wue7f44932021-08-17 20:05:51 +0800177 .time_window_min = 28 * MSECS_PER_SEC,
178 .time_window_max = 32 * MSECS_PER_SEC,
179 .granularity = 200,
180 },
181 .pl2 = {
David Wu6555c4c2022-03-01 13:59:20 +0800182 .min_power = 43000,
183 .max_power = 43000,
David Wue7f44932021-08-17 20:05:51 +0800184 .time_window_min = 28 * MSECS_PER_SEC,
185 .time_window_max = 32 * MSECS_PER_SEC,
186 .granularity = 1000,
187 }
188 }"
189
190 ## Charger Performance Control (Control, mA)
191 register "controls.charger_perf" = "{
192 [0] = { 255, 1700 },
193 [1] = { 24, 1500 },
194 [2] = { 16, 1000 },
195 [3] = { 8, 500 }
196 }"
197
198 ## Fan Performance Control (Percent, Speed, Noise, Power)
199 register "controls.fan_perf" = "{
200 [0] = { 90, 6700, 220, 2200, },
201 [1] = { 80, 5800, 180, 1800, },
202 [2] = { 70, 5000, 145, 1450, },
203 [3] = { 60, 4900, 115, 1150, },
204 [4] = { 50, 3838, 90, 900, },
205 [5] = { 40, 2904, 55, 550, },
206 [6] = { 30, 2337, 30, 300, },
207 [7] = { 20, 1608, 15, 150, },
208 [8] = { 10, 800, 10, 100, },
209 [9] = { 0, 0, 0, 50, }
210 }"
211
212 ## Fan options
213 register "options.fan.fine_grained_control" = "1"
214 register "options.fan.step_size" = "2"
215
Furquan Shaikh4aba7392021-09-20 10:51:45 -0700216 device generic 0 alias dptf_policy on end
David Wue7f44932021-08-17 20:05:51 +0800217 end
218 end
David Wu215ff5d2021-09-11 09:46:18 +0800219 device ref ipu on
220 chip drivers/intel/mipi_camera
221 register "acpi_uid" = "0x50000"
222 register "acpi_name" = ""IPU0""
223 register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
224
225 register "cio2_num_ports" = "1"
226 register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
227 register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
Lai, Jimae9a8442021-09-30 13:39:58 +0800228 register "cio2_prt[0]" = "1"
David Wueea22f62021-10-26 19:13:54 +0800229 device generic 0 on
230 probe UFC UFC_MIPI_OVTI2740
David Wucedd4d12022-12-16 20:53:49 +0800231 probe ZYDRON_UFC UFC_MIPI_HI556
232 probe ZYDRON_UFC UFC_MIPI_OVTI2740
David Wueea22f62021-10-26 19:13:54 +0800233 end
David Wu215ff5d2021-09-11 09:46:18 +0800234 end
235 end
David Wue7f44932021-08-17 20:05:51 +0800236 device ref pcie4_0 on
237 # Enable CPU PCIE RP 1 using CLK 0
238 register "cpu_pcie_rp[CPU_RP(1)]" = "{
239 .clk_req = 0,
240 .clk_src = 0,
Tracy Wuec877d62022-01-13 21:53:02 +0800241 .flags = PCIE_RP_LTR | PCIE_RP_AER,
David Wue7f44932021-08-17 20:05:51 +0800242 }"
243 end
244 device ref tcss_dma0 on
245 chip drivers/intel/usb4/retimer
246 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
247 use tcss_usb3_port1 as dfp[0].typec_port
248 device generic 0 on end
249 end
250 end
251 device ref tcss_dma1 on
252 chip drivers/intel/usb4/retimer
253 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
254 use tcss_usb3_port3 as dfp[0].typec_port
255 device generic 0 on end
256 end
257 end
258 device ref cnvi_wifi on
259 chip drivers/wifi/generic
260 register "wake" = "GPE0_PME_B0"
261 device generic 0 on end
262 end
263 end
264 device ref i2c0 on
265 chip drivers/i2c/nau8825
266 register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
267 register "jkdet_enable" = "1"
268 register "jkdet_pull_enable" = "0"
269 register "jkdet_pull_up" = "0"
270 register "jkdet_polarity" = "1" # ActiveLow
271 register "vref_impedance" = "2" # 125kOhm
272 register "micbias_voltage" = "6" # 2.754
273 register "sar_threshold_num" = "4"
274 register "sar_threshold[0]" = "0x0C"
275 register "sar_threshold[1]" = "0x1C"
276 register "sar_threshold[2]" = "0x38"
277 register "sar_threshold[3]" = "0x60"
278 register "sar_hysteresis" = "1"
279 register "sar_voltage" = "6"
280 register "sar_compare_time" = "0" # 500ns
281 register "sar_sampling_time" = "0" # 2us
282 register "short_key_debounce" = "2" # 100ms
283 register "jack_insert_debounce" = "7" # 512ms
284 register "jack_eject_debounce" = "7" # 512ms
285 device i2c 1a on
286 probe AUDIO MAX98373_NAU88L25B_I2S
287 end
288 end
David Wuf0d9c122021-09-24 09:20:17 +0800289 chip drivers/i2c/max98373
290 register "vmon_slot_no" = "0"
291 register "imon_slot_no" = "1"
292 register "uid" = "0"
293 register "desc" = ""Right Speaker Amp""
294 register "name" = ""MAXR""
295 device i2c 31 on
296 probe AUDIO MAX98373_NAU88L25B_I2S
297 end
298 end
299 chip drivers/i2c/max98373
300 register "vmon_slot_no" = "2"
301 register "imon_slot_no" = "3"
302 register "uid" = "1"
303 register "desc" = ""Left Speaker Amp""
304 register "name" = ""MAXL""
305 device i2c 32 on
306 probe AUDIO MAX98373_NAU88L25B_I2S
307 end
308 end
David Wue7f44932021-08-17 20:05:51 +0800309 end #I2C0
310 device ref i2c1 on
David Wu02cef7a2021-11-23 11:26:44 +0800311 chip drivers/i2c/tpm
312 register "hid" = ""GOOG0005""
313 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
314 device i2c 50 on end
David Wu6db243a2021-11-09 12:36:43 +0800315 end
David Wue7f44932021-08-17 20:05:51 +0800316 end
317 device ref i2c2 on
David Wu215ff5d2021-09-11 09:46:18 +0800318 chip drivers/intel/mipi_camera
Lai, Jimae9a8442021-09-30 13:39:58 +0800319 register "acpi_hid" = ""INT3474""
David Wu215ff5d2021-09-11 09:46:18 +0800320 register "acpi_uid" = "0"
321 register "acpi_name" = ""CAM0""
322 register "chip_name" = ""Ov 2740 Camera""
323 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
324 register "has_power_resource" = "1"
325
326 register "ssdb.lanes_used" = "2"
327 register "ssdb.link_used" = "1"
328 register "num_freq_entries" = "1"
Lai, Jimae9a8442021-09-30 13:39:58 +0800329 register "link_freq[0]" = "360 * MHz"
David Wu215ff5d2021-09-11 09:46:18 +0800330 register "remote_name" = ""IPU0""
Jim Lai77426ff2022-01-13 15:22:38 +0800331 register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
David Wu215ff5d2021-09-11 09:46:18 +0800332
333 #Controls
334 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
335 register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
336
337 register "gpio_panel.gpio[0].gpio_num" = "GPP_F20" #reset
338 register "gpio_panel.gpio[1].gpio_num" = "GPP_C4" #power
339
340 #_ON
341 register "on_seq.ops_cnt" = "4"
342 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
343 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
344 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
345 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
346
347 #_OFF
348 register "off_seq.ops_cnt" = "3"
349 register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
350 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
351 register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
352
David Wueea22f62021-10-26 19:13:54 +0800353 device i2c 36 on
354 probe UFC UFC_MIPI_OVTI2740
David Wucedd4d12022-12-16 20:53:49 +0800355 probe ZYDRON_UFC UFC_MIPI_OVTI2740
David Wueea22f62021-10-26 19:13:54 +0800356 end
David Wu215ff5d2021-09-11 09:46:18 +0800357 end
358 chip drivers/intel/mipi_camera
David Wu4a7a0e92022-10-26 16:55:43 +0800359 register "acpi_hid" = ""INT3537""
360 register "acpi_uid" = "0"
361 register "acpi_name" = ""CAM0""
362 register "chip_name" = ""Hi-556 Camera""
363 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
364 register "has_power_resource" = "1"
365
366 register "ssdb.lanes_used" = "2"
367 register "ssdb.link_used" = "1"
368 register "num_freq_entries" = "1"
369 register "link_freq[0]" = "437 * MHz" # 437 MHz
370 register "remote_name" = ""IPU0""
371 register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
372
373 #Controls
374 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
375 register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
376
377 register "gpio_panel.gpio[0].gpio_num" = "GPP_C4" #power
378 register "gpio_panel.gpio[1].gpio_num" = "GPP_F20" #reset
379
380 #_ON
381 register "on_seq.ops_cnt" = "4"
382 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
383 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
384 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
385 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
386
387 #_OFF
388 register "off_seq.ops_cnt" = "3"
389 register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
390 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
391 register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
392
393 device i2c 20 on
David Wucedd4d12022-12-16 20:53:49 +0800394 probe ZYDRON_UFC UFC_MIPI_HI556
David Wu4a7a0e92022-10-26 16:55:43 +0800395 end
396 end
397 chip drivers/intel/mipi_camera
David Wu215ff5d2021-09-11 09:46:18 +0800398 register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
399 register "acpi_uid" = "1"
400 register "acpi_name" = ""NVM0""
401 register "chip_name" = ""AT24 EEPROM""
402 register "device_type" = "INTEL_ACPI_CAMERA_NVM"
403
David Wu215ff5d2021-09-11 09:46:18 +0800404 register "nvm_size" = "0x2000"
405 register "nvm_pagesize" = "1"
406 register "nvm_readonly" = "1"
407 register "nvm_width" = "0x10"
408 register "nvm_compat" = ""atmel,24c64""
409
David Wueea22f62021-10-26 19:13:54 +0800410 device i2c 50 on
411 probe UFC UFC_MIPI_OVTI2740
David Wucedd4d12022-12-16 20:53:49 +0800412 probe ZYDRON_UFC UFC_MIPI_HI556
413 probe ZYDRON_UFC UFC_MIPI_OVTI2740
David Wueea22f62021-10-26 19:13:54 +0800414 end
David Wu215ff5d2021-09-11 09:46:18 +0800415 end
David Wue7f44932021-08-17 20:05:51 +0800416 end
David Wu6de48982021-11-18 21:22:33 +0800417 device ref i2c3 on
David Wu02cef7a2021-11-23 11:26:44 +0800418 chip drivers/i2c/hid
419 register "generic.hid" = ""ELAN90FC""
420 register "generic.desc" = ""ELAN Touchscreen""
421 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
Matt DeVillier8a0e6b52023-04-27 10:04:27 -0500422 register "generic.detect" = "1"
David Wu02cef7a2021-11-23 11:26:44 +0800423 register "generic.reset_gpio" =
424 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
David Wudb4b71f2023-02-04 16:32:04 +0800425 register "generic.reset_delay_ms" = "150"
David Wu02cef7a2021-11-23 11:26:44 +0800426 register "generic.reset_off_delay_ms" = "1"
427 register "generic.enable_gpio" =
428 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
429 register "generic.enable_delay_ms" = "6"
David Wu6179f7b2022-02-23 13:25:05 +0800430 register "generic.enable_off_delay_ms" = "30"
David Wu02cef7a2021-11-23 11:26:44 +0800431 register "generic.stop_gpio" =
432 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
433 register "generic.stop_off_delay_ms" = "1"
434 register "generic.has_power_resource" = "1"
435 register "hid_desc_reg_offset" = "0x01"
436 device i2c 0x10 on end
437 end
438 chip drivers/generic/gpio_keys
439 register "name" = ""PENH""
440 # GPP_D6 is the IRQ source, and GPP_D17 is the wake source
441 register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)"
442 register "key.wake_gpe" = "GPE0_DW1_17"
443 register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
444 register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
445 register "key.dev_name" = ""EJCT""
446 register "key.linux_code" = "SW_PEN_INSERTED"
447 register "key.linux_input_type" = "EV_SW"
448 register "key.label" = ""pen_eject""
David Wua5b6ec02021-12-27 13:50:27 +0800449 device generic 0 on
450 probe STYLUS STYLUS_PRESENT
451 end
David Wu6de48982021-11-18 21:22:33 +0800452 end
453 end
David Wue7f44932021-08-17 20:05:51 +0800454 device ref i2c5 on
455 chip drivers/i2c/generic
456 register "hid" = ""ELAN0000""
457 register "desc" = ""ELAN Touchpad""
458 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
459 register "wake" = "GPE0_DW2_14"
Matt DeVillier2cf52d82022-09-01 15:09:24 -0500460 register "detect" = "1"
David Wue7f44932021-08-17 20:05:51 +0800461 device i2c 15 on end
462 end
David Wu16e815f2021-09-29 12:54:58 +0800463 chip drivers/i2c/hid
Matt DeVilliere9f0ed52022-12-19 15:06:15 -0600464 register "generic.hid" = ""SYNA0000""
465 register "generic.cid" = ""ACPI0C50""
David Wu16e815f2021-09-29 12:54:58 +0800466 register "generic.desc" = ""Synaptics Touchpad""
467 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
468 register "generic.wake" = "GPE0_DW2_14"
Matt DeVillier2cf52d82022-09-01 15:09:24 -0500469 register "generic.detect" = "1"
David Wu16e815f2021-09-29 12:54:58 +0800470 register "hid_desc_reg_offset" = "0x20"
471 device i2c 0x2c on end
472 end
David Wue7f44932021-08-17 20:05:51 +0800473 end
David Wu1bdf09d2021-10-25 11:54:41 +0800474 device ref pcie_rp6 off end # PCIE6 WWAN
475 device ref pcie_rp8 off end # PCIE8 SD card
476 device ref pcie_rp9 off end # PCIE9-12 SSD
David Wue7f44932021-08-17 20:05:51 +0800477 device ref gspi1 on
478 chip drivers/spi/acpi
479 register "name" = ""CRFP""
480 register "hid" = "ACPI_DT_NAMESPACE_HID"
481 register "uid" = "1"
482 register "compat_string" = ""google,cros-ec-spi""
483 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
484 register "wake" = "GPE0_DW2_15"
Tarun Tuli2b523ce2022-08-29 13:39:58 -0400485 register "has_power_resource" = "1"
486 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
487 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
488 register "enable_delay_ms" = "3"
Matt DeVillieraf46b472023-10-28 11:16:14 -0500489 device spi 0 hidden end
David Wue7f44932021-08-17 20:05:51 +0800490 end # FPMCU
491 end
492 device ref pch_espi on
493 chip ec/google/chromeec
494 use conn0 as mux_conn[0]
495 use conn1 as mux_conn[1]
496 device pnp 0c09.0 on end
497 end
498 end
499 device ref pmc hidden
500 chip drivers/intel/pmc_mux
501 device generic 0 on
502 chip drivers/intel/pmc_mux/conn
Reka Normand448f8c2021-12-09 12:09:27 +1100503 use usb2_port1 as usb2_port
504 use tcss_usb3_port1 as usb3_port
David Wue7f44932021-08-17 20:05:51 +0800505 device generic 0 alias conn0 on end
506 end
507 chip drivers/intel/pmc_mux/conn
Reka Normand448f8c2021-12-09 12:09:27 +1100508 use usb2_port3 as usb2_port
509 use tcss_usb3_port3 as usb3_port
David Wue7f44932021-08-17 20:05:51 +0800510 device generic 1 alias conn1 on end
511 end
512 end
513 end
514 end
515 device ref tcss_xhci on
516 chip drivers/usb/acpi
517 device ref tcss_root_hub on
518 chip drivers/usb/acpi
519 register "desc" = ""USB3 Type-C Port C0 (MLB)""
520 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
Won Chung9c5a1072022-02-02 22:30:53 +0000521 register "use_custom_pld" = "true"
Subrata Banikbf265b42022-02-16 17:31:51 +0530522 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
David Wue7f44932021-08-17 20:05:51 +0800523 device ref tcss_usb3_port1 on end
524 end
525 chip drivers/usb/acpi
526 register "desc" = ""USB3 Type-C Port C1 (MLB)""
527 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
Won Chung9c5a1072022-02-02 22:30:53 +0000528 register "use_custom_pld" = "true"
Won Chungc7e90a52022-05-23 22:42:39 +0000529 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
David Wue7f44932021-08-17 20:05:51 +0800530 device ref tcss_usb3_port3 on end
531 end
532 end
533 end
534 end
535 device ref xhci on
536 chip drivers/usb/acpi
537 device ref xhci_root_hub on
538 chip drivers/usb/acpi
539 register "desc" = ""USB2 Type-C Port C0 (MLB)""
540 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
Won Chung9c5a1072022-02-02 22:30:53 +0000541 register "use_custom_pld" = "true"
Subrata Banikbf265b42022-02-16 17:31:51 +0530542 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
David Wue7f44932021-08-17 20:05:51 +0800543 device ref usb2_port1 on end
544 end
545 chip drivers/usb/acpi
546 register "desc" = ""USB2 Type-C Port C1 (MLB)""
547 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
Won Chung9c5a1072022-02-02 22:30:53 +0000548 register "use_custom_pld" = "true"
Won Chungc7e90a52022-05-23 22:42:39 +0000549 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
David Wue7f44932021-08-17 20:05:51 +0800550 device ref usb2_port3 on end
551 end
552 chip drivers/usb/acpi
553 register "desc" = ""USB2 Camera""
554 register "type" = "UPC_TYPE_INTERNAL"
David Wueea22f62021-10-26 19:13:54 +0800555 device ref usb2_port6 on
556 probe UFC UFC_USB
557 end
David Wue7f44932021-08-17 20:05:51 +0800558 end
559 chip drivers/usb/acpi
560 register "desc" = ""USB2 Type-A Port A0 (MLB)""
561 register "type" = "UPC_TYPE_A"
Won Chung9c5a1072022-02-02 22:30:53 +0000562 register "use_custom_pld" = "true"
Won Chungc7e90a52022-05-23 22:42:39 +0000563 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
David Wue7f44932021-08-17 20:05:51 +0800564 device ref usb2_port9 on end
565 end
566 chip drivers/usb/acpi
567 register "desc" = ""USB2 Bluetooth""
568 register "type" = "UPC_TYPE_INTERNAL"
569 register "reset_gpio" =
570 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
571 device ref usb2_port10 on end
572 end
573 chip drivers/usb/acpi
574 register "desc" = ""USB3 Type-A Port A0 (MLB)""
575 register "type" = "UPC_TYPE_USB3_A"
Won Chung9c5a1072022-02-02 22:30:53 +0000576 register "use_custom_pld" = "true"
Won Chungc7e90a52022-05-23 22:42:39 +0000577 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
David Wue7f44932021-08-17 20:05:51 +0800578 device ref usb3_port1 on end
579 end
580 end
581 end
582 end
Matt DeVillier3f3dc502023-01-17 13:44:23 -0600583 device ref hda on
584 chip drivers/sof
585 register "spkr_tplg" = "max98373"
586 register "jack_tplg" = "nau8825"
587 register "mic_tplg" = "_2ch_pdm0"
588 device generic 0 on end
589 end
590 end
David Wue7f44932021-08-17 20:05:51 +0800591 end
David Wu07375cb2021-07-08 10:58:00 +0800592end