| Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 3 | |
| 4 | /* Note: Only need HID on Primary Bus */ |
| 5 | External (TOM1) |
| 6 | External (TOM2) |
| 7 | Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ |
| 8 | Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ |
| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 9 | |
| 10 | /* Describe the Northbridge devices */ |
| 11 | |
| 12 | Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ |
| 13 | { |
| 14 | Return(Zero) |
| 15 | } |
| 16 | |
| 17 | Method(_STA, 0, NotSerialized) |
| 18 | { |
| 19 | Return(0x0B) /* Status is visible */ |
| 20 | } |
| 21 | |
| 22 | Method(_PRT,0, NotSerialized) |
| 23 | { |
| 24 | If(PMOD) |
| 25 | { |
| 26 | Return(APR0) /* APIC mode */ |
| 27 | } |
| 28 | Return (PR0) /* PIC Mode */ |
| 29 | } |
| 30 | |
| 31 | Device(AMRT) { |
| 32 | Name(_ADR, 0x00000000) |
| 33 | } /* end AMRT */ |
| 34 | |
| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 35 | /* Internal Graphics */ |
| 36 | Device(IGFX) { |
| 37 | Name(_ADR, 0x00010000) |
| 38 | } |
| 39 | |
| 40 | /* Gpp 0 */ |
| 41 | Device(PBR4) { |
| 42 | Name(_ADR, 0x00020001) |
| 43 | Method(_PRT,0) { |
| 44 | If(PMOD){ Return(APS4) } /* APIC mode */ |
| 45 | Return (PS4) /* PIC Mode */ |
| 46 | } /* end _PRT */ |
| 47 | } /* end PBR4 */ |
| 48 | |
| 49 | /* Gpp 1 */ |
| 50 | Device(PBR5) { |
| 51 | Name(_ADR, 0x00020002) |
| 52 | Method(_PRT,0) { |
| 53 | If(PMOD){ Return(APS5) } /* APIC mode */ |
| 54 | Return (PS5) /* PIC Mode */ |
| 55 | } /* end _PRT */ |
| 56 | } /* end PBR5 */ |
| 57 | |
| 58 | /* Gpp 2 */ |
| 59 | Device(PBR6) { |
| 60 | Name(_ADR, 0x00020003) |
| 61 | Method(_PRT,0) { |
| 62 | If(PMOD){ Return(APS6) } /* APIC mode */ |
| 63 | Return (PS6) /* PIC Mode */ |
| 64 | } /* end _PRT */ |
| 65 | } /* end PBR6 */ |
| 66 | |
| 67 | /* Gpp 3 */ |
| 68 | Device(PBR7) { |
| 69 | Name(_ADR, 0x00020004) |
| 70 | Method(_PRT,0) { |
| 71 | If(PMOD){ Return(APS7) } /* APIC mode */ |
| 72 | Return (PS7) /* PIC Mode */ |
| 73 | } /* end _PRT */ |
| 74 | } /* end PBR7 */ |
| 75 | |
| 76 | /* Gpp 4 */ |
| 77 | Device(PBR8) { |
| 78 | Name(_ADR, 0x00020005) |
| 79 | Method(_PRT,0) { |
| 80 | If(PMOD){ Return(APS8) } /* APIC mode */ |
| 81 | Return (PS8) /* PIC Mode */ |
| 82 | } /* end _PRT */ |
| 83 | } /* end PBR8 */ |
| 84 | |
| 85 | Device(AZHD) { /* 0:9.2 - HD Audio */ |
| 86 | Name(_ADR, 0x00090002) |
| 87 | OperationRegion(AZPD, PCI_Config, 0x00, 0x100) |
| 88 | Field(AZPD, AnyAcc, NoLock, Preserve) { |
| 89 | offset (0x42), |
| 90 | NSDI, 1, |
| 91 | NSDO, 1, |
| 92 | NSEN, 1, |
| 93 | offset (0x44), |
| 94 | IPCR, 4, |
| 95 | offset (0x54), |
| 96 | PWST, 2, |
| 97 | , 6, |
| 98 | PMEB, 1, |
| 99 | , 6, |
| 100 | PMST, 1, |
| 101 | offset (0x62), |
| 102 | MMCR, 1, |
| 103 | offset (0x64), |
| 104 | MMLA, 32, |
| 105 | offset (0x68), |
| 106 | MMHA, 32, |
| 107 | offset (0x6c), |
| 108 | MMDT, 16, |
| 109 | } |
| 110 | |
| 111 | Method (_INI, 0, NotSerialized) |
| 112 | { |
| 113 | If (LEqual (OSVR, 0x03)) |
| 114 | { |
| 115 | Store (Zero, NSEN) |
| 116 | Store (One, NSDO) |
| 117 | Store (One, NSDI) |
| 118 | } |
| 119 | } |
| 120 | } /* end AZHD */ |