Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 15 | #define __SIMPLE_DEVICE__ |
| 16 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 17 | #include <arch/romstage.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci_def.h> |
| 21 | #include <console/console.h> |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 22 | #include <cbmem.h> |
| 23 | #include <northbridge/intel/pineview/pineview.h> |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 24 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 25 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 26 | #include <cpu/intel/smm_reloc.h> |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 27 | #include <stdint.h> |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 28 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 29 | u8 decode_pciebar(u32 *const base, u32 *const len) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 30 | { |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 31 | *base = 0; |
| 32 | *len = 0; |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 33 | const pci_devfn_t dev = HOST_BRIDGE; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 34 | u32 pciexbar = 0; |
| 35 | u32 pciexbar_reg; |
| 36 | u32 reg32; |
| 37 | int max_buses; |
| 38 | const struct { |
| 39 | u16 num_buses; |
| 40 | u32 addr_mask; |
| 41 | } busmask[] = { |
| 42 | {256, 0xf0000000}, |
| 43 | {128, 0xf8000000}, |
| 44 | {64, 0xfc000000}, |
| 45 | {0, 0}, |
| 46 | }; |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 47 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 48 | pciexbar_reg = pci_read_config32(dev, PCIEXBAR); |
| 49 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 50 | /* MMCFG not supported or not enabled */ |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 51 | if (!(pciexbar_reg & (1 << 0))) { |
| 52 | printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); |
| 53 | return 0; |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 54 | } |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 55 | |
| 56 | reg32 = (pciexbar_reg >> 1) & 3; |
| 57 | pciexbar = pciexbar_reg & busmask[reg32].addr_mask; |
| 58 | max_buses = busmask[reg32].num_buses; |
| 59 | |
| 60 | if (!pciexbar) { |
| 61 | printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); |
| 62 | return 0; |
| 63 | } |
| 64 | |
| 65 | *base = pciexbar; |
| 66 | *len = max_buses << 20; |
| 67 | return 1; |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 68 | } |
| 69 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 70 | /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ |
| 71 | u32 decode_igd_memory_size(const u32 gms) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 72 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 73 | const u32 gmssize[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256}; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 74 | |
| 75 | if (gms > 9) { |
| 76 | printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) value.\n"); |
| 77 | return 0; |
| 78 | } |
| 79 | return gmssize[gms] << 10; |
| 80 | } |
| 81 | |
| 82 | /** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ |
| 83 | u32 decode_igd_gtt_size(const u32 gsm) |
| 84 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 85 | const u8 gsmsize[] = {0, 1, 0, 0}; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 86 | |
| 87 | if (gsm > 3) { |
| 88 | printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) value.\n"); |
| 89 | return 0; |
| 90 | } |
| 91 | return (u32)(gsmsize[gsm] << 10); |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 92 | } |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 93 | |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 94 | /** Decodes used TSEG size to bytes. */ |
| 95 | static u32 decode_tseg_size(const u32 esmramc) |
| 96 | { |
| 97 | if (!(esmramc & 1)) |
| 98 | return 0; |
| 99 | |
| 100 | switch ((esmramc >> 1) & 3) { |
| 101 | case 0: |
| 102 | return 1 << 20; |
| 103 | case 1: |
| 104 | return 2 << 20; |
| 105 | case 2: |
| 106 | return 8 << 20; |
| 107 | case 3: |
| 108 | default: |
| 109 | die("Bad TSEG setting.\n"); |
| 110 | } |
| 111 | } |
| 112 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 113 | static size_t northbridge_get_tseg_size(void) |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 114 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 115 | const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 116 | return decode_tseg_size(esmramc); |
| 117 | } |
| 118 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 119 | static uintptr_t northbridge_get_tseg_base(void) |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 120 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 121 | return pci_read_config32(HOST_BRIDGE, TSEG); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 125 | /* |
| 126 | * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. |
| 127 | * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 128 | */ |
Arthur Heymans | 340e4b8 | 2019-10-23 17:25:58 +0200 | [diff] [blame] | 129 | void *cbmem_top_chipset(void) |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 130 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 131 | return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); |
Arthur Heymans | de6bda6 | 2018-04-10 13:40:39 +0200 | [diff] [blame] | 132 | |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 133 | } |
| 134 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 135 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 136 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 137 | *start = northbridge_get_tseg_base(); |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 138 | *size = northbridge_get_tseg_size(); |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 139 | } |
| 140 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 141 | void fill_postcar_frame(struct postcar_frame *pcf) |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 142 | { |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 143 | uintptr_t top_of_ram; |
| 144 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 145 | /* |
| 146 | * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both |
| 147 | * CBMEM and the TSEG region. |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 148 | */ |
| 149 | top_of_ram = (uintptr_t)cbmem_top(); |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 150 | postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); |
| 151 | postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), |
| 152 | MTRR_TYPE_WRBACK); |
Arthur Heymans | 62e784b | 2017-04-21 15:54:44 +0200 | [diff] [blame] | 153 | } |