Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; version 2 of |
| 8 | * the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 16 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 17 | #include "haswell.h" |
| 18 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | void intel_northbridge_haswell_finalize_smm(void) |
| 20 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 21 | pci_or_config16(HOST_BRIDGE, 0x50, 1 << 0); /* GGC */ |
| 22 | pci_or_config32(HOST_BRIDGE, 0x5c, 1 << 0); /* DPR */ |
| 23 | pci_or_config32(HOST_BRIDGE, 0x78, 1 << 10); /* ME */ |
| 24 | pci_or_config32(HOST_BRIDGE, 0x90, 1 << 0); /* REMAPBASE */ |
| 25 | pci_or_config32(HOST_BRIDGE, 0x98, 1 << 0); /* REMAPLIMIT */ |
| 26 | pci_or_config32(HOST_BRIDGE, 0xa0, 1 << 0); /* TOM */ |
| 27 | pci_or_config32(HOST_BRIDGE, 0xa8, 1 << 0); /* TOUUD */ |
| 28 | pci_or_config32(HOST_BRIDGE, 0xb0, 1 << 0); /* BDSM */ |
| 29 | pci_or_config32(HOST_BRIDGE, 0xb4, 1 << 0); /* BGSM */ |
| 30 | pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ |
| 31 | pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 33 | MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ |
| 34 | MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ |
| 35 | MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ |
| 36 | MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ |
| 37 | MCHBAR32_OR(REQLIM, 1UL << 31); |
| 38 | MCHBAR32_OR(DMIVCLIM, 1UL << 31); |
| 39 | MCHBAR32_OR(CRDTLCK, 1 << 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | |
| 41 | /* Memory Controller Lockdown */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 42 | MCHBAR8(MC_LOCK) = 0x8f; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | |
| 44 | /* Read+write the following */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 45 | MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); |
| 46 | MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); |
| 47 | MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 48 | } |