| Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #ifndef _AMD_00630F01_PCI_DEVS_H_ |
| 16 | #define _AMD_00630F01_PCI_DEVS_H_ |
| 17 | |
| 18 | #define BUS0 0 |
| 19 | |
| 20 | /* Graphics and Display */ |
| 21 | #define GFX_DEV 0x1 |
| 22 | #define GFX_FUNC 0 |
| 23 | #define GFX_DEVID 0x1304 |
| 24 | #define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC) |
| 25 | #define PIRQ_GFX FCH_INT_TABLE_SIZE |
| 26 | /* Integrated graphics device, must be after the |
| 27 | * last C00/C01 entry |
| 28 | */ |
| 29 | |
| 30 | /* Internal Audio controller */ |
| 31 | #define ACTL_DEV 0x1 |
| 32 | #define ACTL_FUNC 1 |
| 33 | #define ACTL_DEVID 0x1308 |
| 34 | #define ACTL_DEVFN PCI_DEVFN(ACTL_DEV,ACTL_FUNC) |
| 35 | #define PIRQ_ACTL FCH_INT_TABLE_SIZE+1 |
| 36 | /* Integrated HDMI audio device, must be after the |
| 37 | * last C00/C01 entry |
| 38 | */ |
| 39 | |
| 40 | /* PCIe Ports */ |
| 41 | #define NB_GFX_PCIE_PORTS_DEV 0x2 |
| 42 | #define NB_GPP_PCIE_PORTS_DEV 0x3 |
| 43 | #define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_GFX_PCIE_PORTS_DEV,0x01) |
| 44 | #define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_GFX_PCIE_PORTS_DEV,0x02) |
| 45 | #define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x01) |
| 46 | #define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x02) |
| 47 | #define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x03) |
| 48 | #define NB_PCIE_PORT6_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x04) |
| 49 | #define NB_PCIE_PORT7_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x05) |
| 50 | |
| 51 | #endif /* _AMD_00630F01_PCI_DEVS_H_ */ |