blob: cdeb493711da1bd93e65322d87c2545d66a6cacd [file] [log] [blame]
Martin Roth5c354b92019-04-22 14:55:16 -06001/*
2 * This file is part of the coreboot project.
3 *
Martin Roth5c354b92019-04-22 14:55:16 -06004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <console/uart.h>
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -060016#include <commonlib/helpers.h>
Julius Werner55009af2019-12-02 22:03:27 -080017#include <device/mmio.h>
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -060018#include <amdblocks/gpio_banks.h>
19#include <amdblocks/acpimmio.h>
Martin Roth5c354b92019-04-22 14:55:16 -060020#include <soc/southbridge.h>
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -060021#include <soc/gpio.h>
22
23static const struct _uart_info {
24 uintptr_t base;
25 struct soc_amd_gpio mux[2];
26} uart_info[] = {
27 [0] = { APU_UART0_BASE, {
28 PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
29 PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
30 } },
31 [1] = { APU_UART1_BASE, {
32 PAD_NF(GPIO_143, UART1_TXD, PULL_NONE),
33 PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),
34 } },
35 [2] = { APU_UART2_BASE, {
36 PAD_NF(GPIO_137, UART2_TXD, PULL_NONE),
37 PAD_NF(GPIO_135, UART2_RXD, PULL_NONE),
38 } },
39 [3] = { APU_UART3_BASE, {
40 PAD_NF(GPIO_140, UART3_TXD, PULL_NONE),
41 PAD_NF(GPIO_142, UART3_RXD, PULL_NONE),
42 } },
43};
Martin Roth5c354b92019-04-22 14:55:16 -060044
45uintptr_t uart_platform_base(int idx)
46{
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -060047 if (idx < 0 || idx > ARRAY_SIZE(uart_info))
Martin Roth5c354b92019-04-22 14:55:16 -060048 return 0;
49
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -060050 return uart_info[idx].base;
51}
52
53void set_uart_config(int idx)
54{
55 uint32_t uart_ctrl;
56 uint16_t uart_leg;
57
58 if (idx < 0 || idx > ARRAY_SIZE(uart_info))
59 return;
60
61 program_gpios(uart_info[idx].mux, 2);
62
63 if (CONFIG(PICASSO_UART_1_8MZ)) {
64 uart_ctrl = sm_pci_read32(SMB_UART_CONFIG);
65 uart_ctrl |= 1 << (SMB_UART_1_8M_SHIFT + idx);
66 sm_pci_write32(SMB_UART_CONFIG, uart_ctrl);
67 }
68
69 if (CONFIG(PICASSO_UART_LEGACY) && idx != 3) {
70 /* Force 3F8 if idx=0, 2F8 if idx=1, 3E8 if idx=2 */
71
72 /* TODO: make clearer once PPR is updated */
73 uart_leg = (idx << 8) | (idx << 10) | (idx << 12) | (idx << 14);
74 if (idx == 0)
75 uart_leg |= 1 << FCH_LEGACY_3F8_SH;
76 else if (idx == 1)
77 uart_leg |= 1 << FCH_LEGACY_2F8_SH;
78 else if (idx == 2)
79 uart_leg |= 1 << FCH_LEGACY_3E8_SH;
80
81 write16((void *)FCH_UART_LEGACY_DECODE, uart_leg);
82 }
Martin Roth5c354b92019-04-22 14:55:16 -060083}
84
85unsigned int uart_platform_refclk(void)
86{
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -060087 return CONFIG(PICASSO_UART_48MZ) ? 48000000 : 115200 * 16;
Martin Roth5c354b92019-04-22 14:55:16 -060088}