Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * Copyright 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <arch/cache.h> |
| 23 | #include <arch/spintable.h> |
| 24 | #include <cpu/cpu.h> |
| 25 | #include <bootstate.h> |
| 26 | #include <cbmem.h> |
| 27 | #include <console/console.h> |
| 28 | #include <device/device.h> |
| 29 | #include <soc/nvidia/tegra/dc.h> |
| 30 | #include <soc/addressmap.h> |
| 31 | #include <soc/clock.h> |
| 32 | #include <soc/cpu.h> |
| 33 | #include <soc/mc.h> |
| 34 | #include <soc/mtc.h> |
| 35 | #include <soc/nvidia/tegra/apbmisc.h> |
| 36 | #include <string.h> |
| 37 | #include <timer.h> |
| 38 | #include <vendorcode/google/chromeos/chromeos.h> |
Yen Lin | ae3d71a | 2015-06-01 15:32:09 -0700 | [diff] [blame^] | 39 | #include <soc/sdram.h> |
| 40 | #include <soc/sdram_configs.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 41 | |
| 42 | #include "chip.h" |
| 43 | |
| 44 | static void soc_read_resources(device_t dev) |
| 45 | { |
| 46 | unsigned long index = 0; |
| 47 | int i; uintptr_t begin, end; |
| 48 | size_t size; |
| 49 | |
| 50 | for (i = 0; i < CARVEOUT_NUM; i++) { |
| 51 | carveout_range(i, &begin, &size); |
| 52 | if (size == 0) |
| 53 | continue; |
| 54 | reserved_ram_resource(dev, index++, begin * KiB, size * KiB); |
| 55 | } |
| 56 | |
| 57 | memory_in_range_below_4gb(&begin, &end); |
| 58 | size = end - begin; |
| 59 | ram_resource(dev, index++, begin * KiB, size * KiB); |
| 60 | |
| 61 | memory_in_range_above_4gb(&begin, &end); |
| 62 | size = end - begin; |
| 63 | ram_resource(dev, index++, begin * KiB, size * KiB); |
| 64 | } |
| 65 | |
| 66 | static size_t cntrl_total_cpus(void) |
| 67 | { |
| 68 | return CONFIG_MAX_CPUS; |
| 69 | } |
| 70 | |
| 71 | static int cntrl_start_cpu(unsigned int id, void (*entry)(void)) |
| 72 | { |
| 73 | if (id >= CONFIG_MAX_CPUS) |
| 74 | return -1; |
| 75 | start_cpu(id, entry); |
| 76 | return 0; |
| 77 | } |
| 78 | |
| 79 | static struct cpu_control_ops cntrl_ops = { |
| 80 | .total_cpus = cntrl_total_cpus, |
| 81 | .start_cpu = cntrl_start_cpu, |
| 82 | }; |
| 83 | |
| 84 | |
| 85 | static void lock_down_vpr(void) |
| 86 | { |
| 87 | struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; |
| 88 | |
| 89 | write32(®s->video_protect_bom, 0); |
| 90 | write32(®s->video_protect_size_mb, 0); |
| 91 | |
| 92 | write32(®s->video_protect_gpu_override_0, 1); |
| 93 | /* |
| 94 | * Set both _ACCESS bits so that kernel/secure code |
| 95 | * can reconfig VPR careveout as needed from the TrustZone. |
| 96 | */ |
| 97 | |
| 98 | write32(®s->video_protect_reg_ctrl, |
| 99 | (MC_VPR_WR_ACCESS_DISABLE | MC_VPR_ALLOW_TZ_WR_ACCESS_ENABLE)); |
| 100 | } |
| 101 | |
| 102 | static void soc_init(device_t dev) |
| 103 | { |
| 104 | struct soc_nvidia_tegra210_config *cfg; |
| 105 | |
| 106 | clock_init_arm_generic_timer(); |
| 107 | |
| 108 | cfg = dev->chip_info; |
| 109 | spintable_init((void *)cfg->spintable_addr); |
| 110 | arch_initialize_cpus(dev, &cntrl_ops); |
| 111 | |
| 112 | /* Lock down VPR */ |
| 113 | lock_down_vpr(); |
| 114 | |
| 115 | #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) |
| 116 | if (vboot_skip_display_init()) |
| 117 | printk(BIOS_INFO, "Skipping display init.\n"); |
| 118 | else |
| 119 | display_startup(dev); |
| 120 | #endif |
| 121 | } |
| 122 | |
| 123 | static void soc_noop(device_t dev) |
| 124 | { |
| 125 | } |
| 126 | |
| 127 | static struct device_operations soc_ops = { |
| 128 | .read_resources = soc_read_resources, |
| 129 | .set_resources = soc_noop, |
| 130 | .enable_resources = soc_noop, |
| 131 | .init = soc_init, |
| 132 | .scan_bus = NULL, |
| 133 | }; |
| 134 | |
| 135 | static void enable_tegra210_dev(device_t dev) |
| 136 | { |
| 137 | if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 138 | dev->ops = &soc_ops; |
| 139 | } |
| 140 | |
| 141 | static void tegra210_init(void *chip_info) |
| 142 | { |
| 143 | struct tegra_revision rev; |
| 144 | |
| 145 | tegra_revision_info(&rev); |
| 146 | |
| 147 | printk(BIOS_INFO, "chip %x rev %02x.%x\n", |
| 148 | rev.chip_id, rev.major, rev.minor); |
Yen Lin | ae3d71a | 2015-06-01 15:32:09 -0700 | [diff] [blame^] | 149 | |
| 150 | /* Save sdram parameters to scratch regs to be used in LP0 resume */ |
| 151 | sdram_lp0_save_params(get_sdram_config()); |
| 152 | printk(BIOS_INFO, "sdram params saved.\n"); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | struct chip_operations soc_nvidia_tegra210_ops = { |
| 156 | CHIP_NAME("SOC Nvidia Tegra210") |
| 157 | .init = tegra210_init, |
| 158 | .enable_dev = enable_tegra210_dev, |
| 159 | }; |
| 160 | |
| 161 | static void tegra210_cpu_init(device_t cpu) |
| 162 | { |
| 163 | if (cpu_is_bsp()) |
| 164 | if (tegra210_run_mtc() != 0) |
Furquan Shaikh | 5bcf8d6 | 2015-06-16 13:02:40 -0700 | [diff] [blame] | 165 | printk(BIOS_ERR, "MTC: No training data.\n"); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | static const struct cpu_device_id ids[] = { |
| 169 | { 0x411fd071 }, |
| 170 | { CPU_ID_END }, |
| 171 | }; |
| 172 | |
| 173 | static struct device_operations cpu_dev_ops = { |
| 174 | .init = tegra210_cpu_init, |
| 175 | }; |
| 176 | |
| 177 | static const struct cpu_driver driver __cpu_driver = { |
| 178 | .ops = &cpu_dev_ops, |
| 179 | .id_table = ids, |
| 180 | }; |
| 181 | |
| 182 | static void enable_plld(void *unused) |
| 183 | { |
| 184 | /* |
| 185 | * Configure a conservative 300MHz clock for PLLD. The kernel cannot |
| 186 | * handle PLLD not being configured so enable PLLD unconditionally |
| 187 | * with a default clock rate. |
| 188 | */ |
| 189 | clock_configure_plld(300 * MHz); |
| 190 | } |
| 191 | |
| 192 | /* |
| 193 | * The PLLD being enabled is done at BS_DEV_INIT time because mainboard_init() |
| 194 | * is the first thing called. This ensures PLLD is up and functional before |
| 195 | * anything that mainboard can do that implicitly relies on PLLD. |
| 196 | */ |
| 197 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, enable_plld, NULL); |