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review.coreboot.org / coreboot / ad83eb1ee6bb833783c4b870c86413978fb5d4ba / . / src / mainboard / emulation / qemu-sbsa / dsdt.asl
blob: 8280cb7431938bf797d4f30d9a83a1c8a64e257f [file] [log] [blame]
David Milosevicad83eb12023-11-16 05:11:18 +0100[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#define LINK_DEVICE(Uid, LinkName, Irq) \
4 Device (LinkName) { \
5 Name (_HID, EISAID("PNP0C0F")) \
6 Name (_UID, Uid) \
7 Name (_CRS, ResourceTemplate() { \
8 Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \
9 }) \
10 }
11
12#define USB_PORT(PortName, Adr) \
13 Device (PortName) { \
14 Name (_ADR, Adr) \
15 Name (_UPC, Package() { \
16 0xFF, \
17 0x00, \
18 0x00000000, \
19 0x00000000 \
20 }) \
21 Name (_PLD, Package() { \
22 Buffer(0x10) { \
23 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
24 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 \
25 } \
26 }) \
27 }
28
29#define PRT_ENTRY(Address, Pin, Link) \
30 Package (4) { \
31 Address, Pin, Link, Zero \
32 }
33
34#define PRT_ENTRY_GROUP(Address, Link0, Link1, Link2, Link3) \
35 PRT_ENTRY (Address, 0, Link0), \
36 PRT_ENTRY (Address, 1, Link1), \
37 PRT_ENTRY (Address, 2, Link2), \
38 PRT_ENTRY (Address, 3, Link3)
39
40#include <acpi/acpi.h>
41#include <mainboard/addressmap.h>
42
43DefinitionBlock(
44 "dsdt.aml",
45 "DSDT",
46 ACPI_DSDT_REV_2,
47 OEM_ID,
48 ACPI_TABLE_CREATOR,
49 0x20230621
50)
51{
52 #include <acpi/dsdt_top.asl>
53
54 Scope (_SB) {
55 // UART PL011
56 Device (COM0) {
57 Name (_HID, "ARMH0011")
58 Name (_UID, Zero)
59 Name (_CRS, ResourceTemplate () {
60 Memory32Fixed (ReadWrite, SBSA_UART_BASE, 0x00001000)
61 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
62 })
63 }
64
65 // AHCI Host Controller
66 Device (AHC0) {
67 Name (_HID, "LNRO001E")
68 Name (_CLS, Package (3) {
69 0x01,
70 0x06,
71 0x01,
72 })
73 Name (_CCA, 1)
74 Name (_CRS, ResourceTemplate() {
75 Memory32Fixed (ReadWrite, SBSA_AHCI_BASE, 0x00010000)
76 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 }
77 })
78 }
79
80 // USB EHCI Host Controller
81 Device (USB0) {
82 Name (_HID, "LNRO0D20")
83 Name (_CID, "PNP0D20")
84 Method (_CRS, 0x0, Serialized) {
85 Name (RBUF, ResourceTemplate() {
86 Memory32Fixed (ReadWrite, SBSA_EHCI_BASE, 0x00010000)
87 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
88 })
89 Return (RBUF)
90 }
91
92 // Root Hub
93 Device (RHUB) {
94 Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec
95
96 // Ports connected to Root Hub
97 Device (HUB1) {
98 Name (_ADR, 0x00000001)
99 Name (_UPC, Package() {
100 0x00, // Port is NOT connectable
101 0xFF, // Don't care
102 0x00000000, // Reserved 0 must be zero
103 0x00000000 // Reserved 1 must be zero
104 })
105 USB_PORT (PRT1, 0x00000001) // USB0_RHUB_HUB1_PRT1
106 USB_PORT (PRT2, 0x00000002) // USB0_RHUB_HUB1_PRT2
107 USB_PORT (PRT3, 0x00000003) // USB0_RHUB_HUB1_PRT3
108 USB_PORT (PRT4, 0x00000004) // USB0_RHUB_HUB1_PRT4
109 } // USB0_RHUB_HUB1
110 } // USB0_RHUB
111 } // USB0
112
113 Device (PCI0)
114 {
115 Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge
116 Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge
117 Name (_SEG, Zero) // PCI Segment Group number
118 Name (_BBN, Zero) // PCI Base Bus Number
119 Name (_UID, "PCI0")
120 Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1)
121
122 Method (_CBA, 0, NotSerialized) {
123 return (SBSA_PCIE_ECAM_BASE)
124 }
125
126 LINK_DEVICE (0, GSI0, 0x23)
127 LINK_DEVICE (1, GSI1, 0x24)
128 LINK_DEVICE (2, GSI2, 0x25)
129 LINK_DEVICE (3, GSI3, 0x26)
130
131 Name (_PRT, Package () {
132
133 // _PRT: PCI Routing Table
134 PRT_ENTRY_GROUP (0x0000FFFF, GSI0, GSI1, GSI2, GSI3),
135 PRT_ENTRY_GROUP (0x0001FFFF, GSI1, GSI2, GSI3, GSI0),
136 PRT_ENTRY_GROUP (0x0002FFFF, GSI2, GSI3, GSI0, GSI1),
137 PRT_ENTRY_GROUP (0x0003FFFF, GSI3, GSI0, GSI1, GSI2),
138 PRT_ENTRY_GROUP (0x0004FFFF, GSI0, GSI1, GSI2, GSI3),
139 PRT_ENTRY_GROUP (0x0005FFFF, GSI1, GSI2, GSI3, GSI0),
140 PRT_ENTRY_GROUP (0x0006FFFF, GSI2, GSI3, GSI0, GSI1),
141 PRT_ENTRY_GROUP (0x0007FFFF, GSI3, GSI0, GSI1, GSI2),
142 PRT_ENTRY_GROUP (0x0008FFFF, GSI0, GSI1, GSI2, GSI3),
143 PRT_ENTRY_GROUP (0x0009FFFF, GSI1, GSI2, GSI3, GSI0),
144 PRT_ENTRY_GROUP (0x000AFFFF, GSI2, GSI3, GSI0, GSI1),
145 PRT_ENTRY_GROUP (0x000BFFFF, GSI3, GSI0, GSI1, GSI2),
146 PRT_ENTRY_GROUP (0x000CFFFF, GSI0, GSI1, GSI2, GSI3),
147 PRT_ENTRY_GROUP (0x000DFFFF, GSI1, GSI2, GSI3, GSI0),
148 PRT_ENTRY_GROUP (0x000EFFFF, GSI2, GSI3, GSI0, GSI1),
149 PRT_ENTRY_GROUP (0x000FFFFF, GSI3, GSI0, GSI1, GSI2),
150 PRT_ENTRY_GROUP (0x0010FFFF, GSI0, GSI1, GSI2, GSI3),
151 PRT_ENTRY_GROUP (0x0011FFFF, GSI1, GSI2, GSI3, GSI0),
152 PRT_ENTRY_GROUP (0x0012FFFF, GSI2, GSI3, GSI0, GSI1),
153 PRT_ENTRY_GROUP (0x0013FFFF, GSI3, GSI0, GSI1, GSI2),
154 PRT_ENTRY_GROUP (0x0014FFFF, GSI0, GSI1, GSI2, GSI3),
155 PRT_ENTRY_GROUP (0x0015FFFF, GSI1, GSI2, GSI3, GSI0),
156 PRT_ENTRY_GROUP (0x0016FFFF, GSI2, GSI3, GSI0, GSI1),
157 PRT_ENTRY_GROUP (0x0017FFFF, GSI3, GSI0, GSI1, GSI2),
158 PRT_ENTRY_GROUP (0x0018FFFF, GSI0, GSI1, GSI2, GSI3),
159 PRT_ENTRY_GROUP (0x0019FFFF, GSI1, GSI2, GSI3, GSI0),
160 PRT_ENTRY_GROUP (0x001AFFFF, GSI2, GSI3, GSI0, GSI1),
161 PRT_ENTRY_GROUP (0x001BFFFF, GSI3, GSI0, GSI1, GSI2),
162 PRT_ENTRY_GROUP (0x001CFFFF, GSI0, GSI1, GSI2, GSI3),
163 PRT_ENTRY_GROUP (0x001DFFFF, GSI1, GSI2, GSI3, GSI0),
164 PRT_ENTRY_GROUP (0x001EFFFF, GSI2, GSI3, GSI0, GSI1),
165 PRT_ENTRY_GROUP (0x001FFFFF, GSI3, GSI0, GSI1, GSI2),
166 })
167
168 // Root complex resources
169 Method (_CRS, 0, Serialized) {
170 Name (RBUF, ResourceTemplate () {
171 WordBusNumber ( // Bus numbers assigned to this root
172 ResourceProducer,
173 MinFixed, MaxFixed, PosDecode,
174 0, // AddressGranularity
175 0, // AddressMinimum - Minimum Bus Number
176 255, // AddressMaximum - Maximum Bus Number
177 0, // AddressTranslation - Set to 0
178 256 // RangeLength - Number of Busses
179 )
180
181 DWordMemory ( // 32-bit BAR Windows
182 ResourceProducer, PosDecode,
183 MinFixed, MaxFixed,
184 Cacheable, ReadWrite,
185 0x00000000, // Granularity
186 SBSA_PCIE_MMIO_BASE, // Min Base Address
187 SBSA_PCIE_MMIO_LIMIT, // Max Base Address
188 0, // Translate
189 SBSA_PCIE_MMIO_SIZE // Length
190 )
191
192 QWordMemory ( // 64-bit BAR Windows
193 ResourceProducer, PosDecode,
194 MinFixed, MaxFixed,
195 Cacheable, ReadWrite,
196 0x00000000, // Granularity
197 SBSA_PCIE_MMIO_HIGH_BASE, // Min Base Address
198 SBSA_PCIE_MMIO_HIGH_LIMIT, // Max Base Address
199 0, // Translate
200 SBSA_PCIE_MMIO_HIGH_SIZE // Length
201 )
202
203 DWordIo ( // IO window
204 ResourceProducer,
205 MinFixed,
206 MaxFixed,
207 PosDecode,
208 EntireRange,
209 0x00000000, // Granularity
210 0, // Min Base Address
211 0xffff, // Max Base Address
212 SBSA_PCIE_PIO_BASE, // Translate
213 0x10000, // Length
214 ,,,TypeTranslation
215 )
216 }) // Name(RBUF)
217
218 Return (RBUF)
219 } // Method(_CRS)
220
221 // OS Control Handoff
222 Name (SUPP, Zero) // PCI _OSC Support Field value
223 Name (CTRL, Zero) // PCI _OSC Control Field value
224
225 /*
226 * See [1] 6.2.10, [2] 4.5
227 */
228 Method (_OSC,4) {
229 // Check for proper UUID
230 If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
231 // Create DWord-adressable fields from the Capabilities Buffer
232 CreateDWordField (Arg3,0,CDW1)
233 CreateDWordField (Arg3,4,CDW2)
234 CreateDWordField (Arg3,8,CDW3)
235
236 // Save Capabilities DWord2 & 3
237 SUPP = CDW2
238 CTRL = CDW3
239
240 // Only allow native hot plug control if OS supports:
241 // * ASPM
242 // * Clock PM
243 // * MSI/MSI-X
244 If ((SUPP & 0x16) != 0x16) {
245 CTRL &= 0x1E // Mask bit 0 (and undefined bits)
246 }
247
248 // Always allow native PME, AER (no dependencies)
249
250 // Never allow SHPC (no SHPC controller in this system)
251 CTRL &= 0x1D
252
253 If (Arg1 != One) { // Unknown revision
254 CDW1 |= 0x08
255 }
256
257 If (CDW3 != CTRL) { // Capabilities bits were masked
258 CDW1 |= 0x10
259 }
260
261 // Update DWORD3 in the buffer
262 CDW3 = CTRL
263 Return (Arg3)
264 } Else {
265 CDW1 |= 4 // Unrecognized UUID
266 Return (Arg3)
267 }
268 } // End _OSC
269 }
270 } // Scope (_SB)
271}