Gitiles
Code Review Sign In
review.coreboot.org / coreboot / ad6157ebdfddc39b95e388487e00cadd2bbf368b / . / src / southbridge / intel / bd82x6x / elog.c
blob: 684f830a9bd64749909208e99b0da3ca5230b4ff [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Duncan Laurie800e9502012-06-23 17:06:47 -0700[diff] [blame]2
3#include <arch/io.h>
Furquan Shaikh76cedd22020-05-02 10:24:23 -0700[diff] [blame]4#include <acpi/acpi.h>
Duncan Laurie800e9502012-06-23 17:06:47 -0700[diff] [blame]5#include <device/device.h>
6#include <device/pci.h>
7#include <device/pci_ops.h>
8#include <stdint.h>
Duncan Laurie800e9502012-06-23 17:06:47 -0700[diff] [blame]9#include <elog.h>
Arthur Heymansf0a017f2018-12-25 15:26:58 +0100[diff] [blame]10#include <southbridge/intel/common/pmutil.h>
Arthur Heymans68f68882018-04-11 13:03:34 +0200[diff] [blame]11#include "pch.h"
Duncan Laurie800e9502012-06-23 17:06:47 -0700[diff] [blame]12
13void pch_log_state(void)
14{
15 u16 pm1_sts, gen_pmcon_3, tco2_sts;
16 u32 gpe0_sts, gpe0_en;
17 u8 gen_pmcon_2;
18 int i;
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300[diff] [blame]19 struct device *lpc = pcidev_on_root(0x1f, 0);
Duncan Laurie800e9502012-06-23 17:06:47 -0700[diff] [blame]20 if (!lpc)
21 return;
22
23 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
24 gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS);
25 gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN);
26 tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS);
27 gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2);
28 gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
29
30 /* PWR_FLR Power Failure */
31 if (gen_pmcon_2 & (1 << 0))
32 elog_add_event(ELOG_TYPE_POWER_FAIL);
33
34 /* SUS Well Power Failure */
35 if (gen_pmcon_3 & (1 << 14))
36 elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
37
38 /* SYS_PWROK Failure */
39 if (gen_pmcon_2 & (1 << 1))
40 elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
41
42 /* PWROK Failure */
43 if (gen_pmcon_2 & (1 << 0))
44 elog_add_event(ELOG_TYPE_PWROK_FAIL);
45
46 /* Second TCO Timeout */
47 if (tco2_sts & (1 << 1))
48 elog_add_event(ELOG_TYPE_TCO_RESET);
49
50 /* Power Button Override */
51 if (pm1_sts & (1 << 11))
52 elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
53
54 /* System Reset Status (reset button pushed) */
55 if (gen_pmcon_2 & (1 << 4))
56 elog_add_event(ELOG_TYPE_RESET_BUTTON);
57
58 /* General Reset Status */
59 if (gen_pmcon_3 & (1 << 9))
60 elog_add_event(ELOG_TYPE_SYSTEM_RESET);
61
62 /* ACPI Wake */
63 if (pm1_sts & (1 << 15))
64 elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
Kyösti Mälkkic3ed8862014-06-19 19:50:51 +0300[diff] [blame]65 acpi_is_wakeup_s3() ? 3 : 5);
Duncan Laurie800e9502012-06-23 17:06:47 -0700[diff] [blame]66
67 /*
68 * Wake sources
69 */
70
71 /* RTC */
72 if (pm1_sts & (1 << 10))
73 elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
74
75 /* PCI Express (TODO: determine wake device) */
76 if (pm1_sts & (1 << 14))
77 elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
78
79 /* PME (TODO: determine wake device) */
80 if (gpe0_sts & (1 << 13))
81 elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
82
83 /* Internal PME (TODO: determine wake device) */
84 if (gpe0_sts & (1 << 13))
85 elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
86
87 /* GPIO 0-15 */
88 for (i = 0; i < 16; i++) {
89 if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i))))
Aaron Durbinaa902032020-08-17 09:37:13 -0600[diff] [blame]90 elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
Duncan Laurie800e9502012-06-23 17:06:47 -0700[diff] [blame]91 }
92
93 /* SMBUS Wake */
94 if (gpe0_sts & (1 << 7))
95 elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
96}