Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* TODO: Check if this is still correct */ |
| 4 | |
| 5 | #include <amdblocks/aoac.h> |
| 6 | #include <console/console.h> |
| 7 | #include <device/device.h> |
| 8 | #include <device/pci.h> |
| 9 | #include <fsp/api.h> |
| 10 | #include <soc/acpi.h> |
| 11 | #include <soc/aoac_defs.h> |
| 12 | #include <soc/cpu.h> |
| 13 | #include <soc/data_fabric.h> |
| 14 | #include <soc/pci_devs.h> |
| 15 | #include <soc/southbridge.h> |
| 16 | #include <types.h> |
| 17 | #include "chip.h" |
| 18 | |
| 19 | /* Supplied by i2c.c */ |
| 20 | extern struct device_operations soc_amd_i2c_mmio_ops; |
| 21 | /* Supplied by uart.c */ |
| 22 | extern struct device_operations sabrina_uart_mmio_ops; |
| 23 | |
| 24 | struct device_operations cpu_bus_ops = { |
| 25 | .read_resources = noop_read_resources, |
| 26 | .set_resources = noop_set_resources, |
| 27 | .init = mp_cpu_bus_init, |
| 28 | .acpi_fill_ssdt = generate_cpu_entries, |
| 29 | }; |
| 30 | |
| 31 | static const char *soc_acpi_name(const struct device *dev) |
| 32 | { |
| 33 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 34 | return "PCI0"; |
| 35 | |
| 36 | if (dev->path.type != DEVICE_PATH_PCI) |
| 37 | return NULL; |
| 38 | |
| 39 | printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n", |
| 40 | PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); |
| 41 | return NULL; |
| 42 | }; |
| 43 | |
| 44 | static struct device_operations pci_domain_ops = { |
| 45 | .read_resources = pci_domain_read_resources, |
| 46 | .set_resources = pci_domain_set_resources, |
| 47 | .scan_bus = pci_domain_scan_bus, |
| 48 | .acpi_name = soc_acpi_name, |
| 49 | }; |
| 50 | |
| 51 | static void set_mmio_dev_ops(struct device *dev) |
| 52 | { |
| 53 | switch (dev->path.mmio.addr) { |
| 54 | case APU_I2C0_BASE: |
| 55 | case APU_I2C1_BASE: |
| 56 | case APU_I2C2_BASE: |
| 57 | case APU_I2C3_BASE: |
| 58 | dev->ops = &soc_amd_i2c_mmio_ops; |
| 59 | break; |
| 60 | case APU_UART0_BASE: |
| 61 | case APU_UART1_BASE: |
Felix Held | b1fe9de | 2022-01-12 23:18:54 +0100 | [diff] [blame] | 62 | case APU_UART2_BASE: |
| 63 | case APU_UART3_BASE: |
| 64 | case APU_UART4_BASE: |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 65 | dev->ops = &sabrina_uart_mmio_ops; |
| 66 | break; |
| 67 | case APU_EMMC_BASE: |
| 68 | if (!dev->enabled) |
| 69 | power_off_aoac_device(FCH_AOAC_DEV_EMMC); |
| 70 | break; |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | static void enable_dev(struct device *dev) |
| 75 | { |
| 76 | /* Set the operations if it is a special bus type */ |
| 77 | switch (dev->path.type) { |
| 78 | case DEVICE_PATH_DOMAIN: |
| 79 | dev->ops = &pci_domain_ops; |
| 80 | break; |
| 81 | case DEVICE_PATH_CPU_CLUSTER: |
| 82 | dev->ops = &cpu_bus_ops; |
| 83 | break; |
| 84 | case DEVICE_PATH_MMIO: |
| 85 | set_mmio_dev_ops(dev); |
| 86 | break; |
| 87 | default: |
| 88 | break; |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | static void soc_init(void *chip_info) |
| 93 | { |
| 94 | default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; |
| 95 | |
| 96 | fsp_silicon_init(); |
| 97 | |
| 98 | data_fabric_set_mmio_np(); |
| 99 | |
| 100 | fch_init(chip_info); |
| 101 | } |
| 102 | |
| 103 | static void soc_final(void *chip_info) |
| 104 | { |
| 105 | fch_final(chip_info); |
| 106 | } |
| 107 | |
| 108 | struct chip_operations soc_amd_sabrina_ops = { |
| 109 | CHIP_NAME("AMD Sabrina SoC") |
| 110 | .enable_dev = enable_dev, |
| 111 | .init = soc_init, |
| 112 | .final = soc_final |
| 113 | }; |