Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <amdblocks/acpimmio.h> |
| 4 | #include <amdblocks/espi.h> |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 5 | #include <amdblocks/i2c.h> |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 6 | #include <amdblocks/lpc.h> |
Felix Held | bbb8c04 | 2021-04-13 19:36:53 +0200 | [diff] [blame] | 7 | #include <amdblocks/pmlib.h> |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 8 | #include <amdblocks/smbus.h> |
| 9 | #include <amdblocks/spi.h> |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 10 | #include <soc/i2c.h> |
| 11 | #include <soc/southbridge.h> |
| 12 | #include <soc/uart.h> |
| 13 | #include <types.h> |
| 14 | |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 15 | #include "chip.h" |
| 16 | |
Felix Held | 916cd50 | 2021-08-04 17:22:36 +0200 | [diff] [blame] | 17 | /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 18 | static const struct soc_i2c_scl_pin i2c_scl_pins[] = { |
Felix Held | 7bbde76 | 2021-09-08 00:37:30 +0200 | [diff] [blame] | 19 | I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), |
| 20 | I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 21 | /* I2C4 is a peripheral device only */ |
| 22 | }; |
| 23 | |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 24 | static void lpc_configure_decodes(void) |
| 25 | { |
| 26 | if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) |
| 27 | lpc_enable_port80(); |
| 28 | } |
| 29 | |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 30 | static void reset_i2c_peripherals(void) |
| 31 | { |
| 32 | const struct soc_amd_picasso_config *cfg = config_of_soc(); |
| 33 | struct soc_i2c_peripheral_reset_info reset_info; |
| 34 | |
| 35 | reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; |
| 36 | reset_info.i2c_scl = i2c_scl_pins; |
| 37 | reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); |
| 38 | sb_reset_i2c_peripherals(&reset_info); |
| 39 | } |
| 40 | |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 41 | /* Before console init */ |
| 42 | void fch_pre_init(void) |
| 43 | { |
Felix Held | 425e73d | 2021-09-20 16:31:33 +0200 | [diff] [blame] | 44 | /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access |
| 45 | the GPIO registers. */ |
| 46 | enable_acpimmio_decode_pm04(); |
Karthikeyan Ramasubramanian | 2d17ea4 | 2021-10-05 13:57:30 -0600 | [diff] [blame] | 47 | /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 48 | lpc_early_init(); |
Felix Held | 4e379a2 | 2021-10-14 21:43:11 +0200 | [diff] [blame] | 49 | |
| 50 | /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI |
| 51 | interface hasn't already been set up in verstage on PSP */ |
| 52 | if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) |
| 53 | configure_espi_with_mb_hook(); |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 54 | |
| 55 | if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) |
| 56 | lpc_configure_decodes(); |
| 57 | |
| 58 | fch_spi_early_init(); |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 59 | fch_smbus_init(); |
| 60 | fch_enable_cf9_io(); |
| 61 | fch_enable_legacy_io(); |
| 62 | enable_aoac_devices(); |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 63 | reset_i2c_peripherals(); |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 64 | |
| 65 | /* |
| 66 | * On reset Range_0 defaults to enabled. We want to start with a clean |
| 67 | * slate to not have things unexpectedly enabled. |
| 68 | */ |
| 69 | clear_uart_legacy_config(); |
| 70 | |
Felix Held | 0dfaf33 | 2020-12-09 16:25:18 +0100 | [diff] [blame] | 71 | if (CONFIG(AMD_SOC_CONSOLE_UART)) |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 72 | set_uart_config(CONFIG_UART_FOR_CONSOLE); |
Felix Held | 27b295b | 2021-03-25 01:20:41 +0100 | [diff] [blame] | 73 | |
| 74 | /* disable the keyboard reset function before mainboard GPIO setup */ |
| 75 | if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) |
| 76 | fch_disable_kb_rst(); |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | /* After console init */ |
| 80 | void fch_early_init(void) |
| 81 | { |
Felix Held | bbb8c04 | 2021-04-13 19:36:53 +0200 | [diff] [blame] | 82 | pm_set_power_failure_state(); |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 83 | fch_print_pmxc0_status(); |
| 84 | i2c_soc_early_init(); |
Martin Roth | fd078d8 | 2021-08-11 13:27:45 -0600 | [diff] [blame] | 85 | show_spi_speeds_and_modes(); |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 86 | |
| 87 | if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) |
| 88 | lpc_disable_spi_rom_sharing(); |
Felix Held | 187f59a | 2020-12-08 02:25:05 +0100 | [diff] [blame] | 89 | } |