Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 3 | #include <acpi/acpi_device.h> |
Felix Held | dba3fe7 | 2021-02-13 01:05:56 +0100 | [diff] [blame] | 4 | #include <amdblocks/data_fabric.h> |
Felix Held | 4b2464f | 2022-02-23 17:54:20 +0100 | [diff] [blame] | 5 | #include <arch/hpet.h> |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 6 | #include <console/console.h> |
| 7 | #include <cpu/x86/lapic_def.h> |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 8 | #include <device/device.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <device/pci_ids.h> |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 11 | #include <soc/data_fabric.h> |
| 12 | #include <soc/iomap.h> |
Felix Held | bf90b14 | 2020-09-15 16:19:54 +0200 | [diff] [blame] | 13 | #include <types.h> |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 14 | |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 15 | void data_fabric_set_mmio_np(void) |
| 16 | { |
| 17 | /* |
| 18 | * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. |
| 19 | * |
| 20 | * AGESA has already programmed the NB MMIO routing, however nothing |
| 21 | * is yet marked as non-posted. |
| 22 | * |
| 23 | * If there exists an overlapping routing base/limit pair, trim its |
| 24 | * base or limit to avoid the new NP region. If any pair exists |
| 25 | * completely within HPET-LAPIC range, remove it. If any pair surrounds |
| 26 | * HPET-LAPIC, it must be split into two regions. |
| 27 | * |
| 28 | * TODO(b/156296146): Remove the settings from AGESA and allow coreboot |
| 29 | * to own everything. If not practical, consider erasing all settings |
| 30 | * and have coreboot reprogram them. At that time, make the source |
| 31 | * below more flexible. |
| 32 | * * Note that the code relies on the granularity of the HPET and |
| 33 | * LAPIC addresses being sufficiently large that the shifted limits |
| 34 | * +/-1 are always equivalent to the non-shifted values +/-1. |
| 35 | */ |
| 36 | |
| 37 | unsigned int i; |
| 38 | int reg; |
| 39 | uint32_t base, limit, ctrl; |
| 40 | const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; |
Kyösti Mälkki | dea42e0 | 2021-05-31 20:26:16 +0300 | [diff] [blame] | 41 | const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 42 | |
Felix Held | 906f9be | 2021-02-13 20:38:08 +0100 | [diff] [blame] | 43 | data_fabric_print_mmio_conf(); |
| 44 | |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 45 | for (i = 0; i < NUM_NB_MMIO_REGS; i++) { |
| 46 | /* Adjust all registers that overlap */ |
Felix Held | 0a14913 | 2021-02-13 01:22:39 +0100 | [diff] [blame] | 47 | ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); |
Felix Held | d560ad6 | 2021-11-24 11:44:50 +0100 | [diff] [blame] | 48 | if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 49 | continue; /* not enabled */ |
| 50 | |
Felix Held | 0a14913 | 2021-02-13 01:22:39 +0100 | [diff] [blame] | 51 | base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); |
| 52 | limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 53 | |
| 54 | if (base > np_top || limit < np_bot) |
| 55 | continue; /* no overlap at all */ |
| 56 | |
| 57 | if (base >= np_bot && limit <= np_top) { |
Felix Held | 602f93e | 2021-02-13 21:10:08 +0100 | [diff] [blame] | 58 | data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 59 | continue; |
| 60 | } |
| 61 | |
| 62 | if (base < np_bot && limit > np_top) { |
| 63 | /* Split the configured region */ |
Felix Held | 0a14913 | 2021-02-13 01:22:39 +0100 | [diff] [blame] | 64 | data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); |
Felix Held | 602f93e | 2021-02-13 21:10:08 +0100 | [diff] [blame] | 65 | reg = data_fabric_find_unused_mmio_reg(); |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 66 | if (reg < 0) { |
| 67 | /* Although a pair could be freed later, this condition is |
| 68 | * very unusual and deserves analysis. Flag an error and |
| 69 | * leave the topmost part unconfigured. */ |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 70 | printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 71 | continue; |
| 72 | } |
Felix Held | 0a14913 | 2021-02-13 01:22:39 +0100 | [diff] [blame] | 73 | data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); |
| 74 | data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); |
| 75 | data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 76 | continue; |
| 77 | } |
| 78 | |
| 79 | /* If still here, adjust only the base or limit */ |
| 80 | if (base <= np_bot) |
Felix Held | 0a14913 | 2021-02-13 01:22:39 +0100 | [diff] [blame] | 81 | data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 82 | else |
Felix Held | 0a14913 | 2021-02-13 01:22:39 +0100 | [diff] [blame] | 83 | data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 84 | } |
| 85 | |
Felix Held | 602f93e | 2021-02-13 21:10:08 +0100 | [diff] [blame] | 86 | reg = data_fabric_find_unused_mmio_reg(); |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 87 | if (reg < 0) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 88 | printk(BIOS_ERR, "cannot configure region as NP\n"); |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 89 | return; |
| 90 | } |
| 91 | |
Felix Held | 0a14913 | 2021-02-13 01:22:39 +0100 | [diff] [blame] | 92 | data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); |
| 93 | data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); |
| 94 | data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), |
Felix Held | d560ad6 | 2021-11-24 11:44:50 +0100 | [diff] [blame] | 95 | (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP |
| 96 | | DF_MMIO_WE | DF_MMIO_RE); |
Felix Held | 906f9be | 2021-02-13 20:38:08 +0100 | [diff] [blame] | 97 | |
| 98 | data_fabric_print_mmio_conf(); |
Raul E Rangel | 789aefc | 2020-05-11 16:26:35 -0600 | [diff] [blame] | 99 | } |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 100 | |
| 101 | static const char *data_fabric_acpi_name(const struct device *dev) |
| 102 | { |
| 103 | switch (dev->device) { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 104 | case PCI_DID_AMD_FAM17H_MODEL18H_DF0: |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 105 | return "DFD0"; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 106 | case PCI_DID_AMD_FAM17H_MODEL18H_DF1: |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 107 | return "DFD1"; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 108 | case PCI_DID_AMD_FAM17H_MODEL18H_DF2: |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 109 | return "DFD2"; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 110 | case PCI_DID_AMD_FAM17H_MODEL18H_DF3: |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 111 | return "DFD3"; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 112 | case PCI_DID_AMD_FAM17H_MODEL18H_DF4: |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 113 | return "DFD4"; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 114 | case PCI_DID_AMD_FAM17H_MODEL18H_DF5: |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 115 | return "DFD5"; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 116 | case PCI_DID_AMD_FAM17H_MODEL18H_DF6: |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 117 | return "DFD6"; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 118 | case PCI_DID_AMD_FAM17H_MODEL18H_DF7: |
Felix Held | 0151b46 | 2021-02-23 17:08:44 +0100 | [diff] [blame] | 119 | return "DFD7"; |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 120 | default: |
| 121 | printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); |
| 122 | } |
| 123 | |
| 124 | return NULL; |
| 125 | } |
| 126 | |
| 127 | static struct device_operations data_fabric_ops = { |
| 128 | .read_resources = noop_read_resources, |
| 129 | .set_resources = noop_set_resources, |
| 130 | .acpi_name = data_fabric_acpi_name, |
| 131 | .acpi_fill_ssdt = acpi_device_write_pci_dev, |
| 132 | }; |
| 133 | |
| 134 | static const unsigned short pci_device_ids[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 135 | PCI_DID_AMD_FAM17H_MODEL18H_DF0, |
| 136 | PCI_DID_AMD_FAM17H_MODEL18H_DF1, |
| 137 | PCI_DID_AMD_FAM17H_MODEL18H_DF2, |
| 138 | PCI_DID_AMD_FAM17H_MODEL18H_DF3, |
| 139 | PCI_DID_AMD_FAM17H_MODEL18H_DF4, |
| 140 | PCI_DID_AMD_FAM17H_MODEL18H_DF5, |
| 141 | PCI_DID_AMD_FAM17H_MODEL18H_DF6, |
| 142 | PCI_DID_AMD_FAM17H_MODEL18H_DF7, |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 143 | 0 |
| 144 | }; |
| 145 | |
| 146 | static const struct pci_driver data_fabric_driver __pci_driver = { |
| 147 | .ops = &data_fabric_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 148 | .vendor = PCI_VID_AMD, |
Furquan Shaikh | 0c707d4 | 2020-07-08 16:54:40 -0700 | [diff] [blame] | 149 | .devices = pci_device_ids, |
| 150 | }; |