Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 4 | * Copyright (C) 2017-2018 Intel Corporation. |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/acpi.h> |
| 17 | #include <arch/io.h> |
| 18 | #include <console/console.h> |
| 19 | #include <cpu/x86/smm.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <intelblocks/pmc.h> |
| 23 | #include <soc/pci_devs.h> |
| 24 | |
| 25 | /* SoC overrides */ |
| 26 | |
| 27 | /* Fill up PMC resource structure inside SoC directory */ |
| 28 | __attribute__((weak)) int pmc_soc_get_resources( |
| 29 | struct pmc_resource_config *cfg) |
| 30 | { |
| 31 | /* no-op */ |
| 32 | return -1; |
| 33 | } |
| 34 | |
| 35 | /* SoC override PMC initialization */ |
| 36 | __attribute__((weak)) void pmc_soc_init(struct device *dev) |
| 37 | { |
| 38 | /* no-op */ |
| 39 | } |
| 40 | |
| 41 | static void pch_pmc_add_new_resource(struct device *dev, |
| 42 | uint8_t offset, uintptr_t base, size_t size, |
| 43 | unsigned long flags) |
| 44 | { |
| 45 | struct resource *res; |
| 46 | res = new_resource(dev, offset); |
| 47 | res->base = base; |
| 48 | res->size = size; |
| 49 | res->flags = flags; |
| 50 | } |
| 51 | |
| 52 | static void pch_pmc_add_mmio_resources(struct device *dev, |
| 53 | const struct pmc_resource_config *cfg) |
| 54 | { |
| 55 | pch_pmc_add_new_resource(dev, cfg->pwrmbase_offset, |
| 56 | cfg->pwrmbase_addr, cfg->pwrmbase_size, |
| 57 | IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 58 | IORESOURCE_FIXED | IORESOURCE_RESERVE); |
| 59 | } |
| 60 | |
| 61 | static void pch_pmc_add_io_resources(struct device *dev, |
| 62 | const struct pmc_resource_config *cfg) |
| 63 | { |
| 64 | pch_pmc_add_new_resource(dev, cfg->abase_offset, |
| 65 | cfg->abase_addr, cfg->abase_size, |
| 66 | IORESOURCE_IO | IORESOURCE_ASSIGNED | |
| 67 | IORESOURCE_FIXED); |
Hannah Williams | 1177bf5 | 2017-12-13 12:44:26 -0800 | [diff] [blame] | 68 | if (IS_ENABLED(CONFIG_PMC_INVALID_READ_AFTER_WRITE)) { |
| 69 | /* |
| 70 | * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've |
| 71 | * observed cases where the BAR reads back as 0, but the IO |
| 72 | * window is open. This also means that it will not respond |
| 73 | * to PCI probing. |
| 74 | */ |
| 75 | pci_write_config16(dev, cfg->abase_offset, cfg->abase_addr); |
| 76 | /* |
| 77 | * In pci_dev_enable_resources, reading IO SPACE ACCESS bit in |
| 78 | * STATUSCOMMAND register does not read back the written |
| 79 | * value correctly, hence IO access gets disabled. This is |
| 80 | * seen in some PMC devices, hence this code makes sure |
| 81 | * IO access is available. |
| 82 | */ |
| 83 | dev->command |= PCI_COMMAND_IO; |
| 84 | } |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | static void pch_pmc_read_resources(struct device *dev) |
| 88 | { |
| 89 | struct pmc_resource_config pmc_cfg; |
| 90 | struct pmc_resource_config *config = &pmc_cfg; |
| 91 | |
| 92 | if (pmc_soc_get_resources(config) < 0) |
| 93 | die("Unable to get PMC controller resource information!"); |
| 94 | |
| 95 | /* Get the normal PCI resources of this device. */ |
| 96 | pci_dev_read_resources(dev); |
| 97 | |
| 98 | /* Add non-standard MMIO resources. */ |
| 99 | pch_pmc_add_mmio_resources(dev, config); |
| 100 | |
| 101 | /* Add IO resources. */ |
| 102 | pch_pmc_add_io_resources(dev, config); |
| 103 | } |
| 104 | |
| 105 | void pmc_set_acpi_mode(void) |
| 106 | { |
| 107 | if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { |
| 108 | printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); |
| 109 | outb(APM_CNT_ACPI_DISABLE, APM_CNT); |
| 110 | printk(BIOS_DEBUG, "done.\n"); |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | static struct device_operations device_ops = { |
| 115 | .read_resources = &pch_pmc_read_resources, |
| 116 | .set_resources = &pci_dev_set_resources, |
| 117 | .enable_resources = &pci_dev_enable_resources, |
| 118 | .init = &pmc_soc_init, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 119 | .ops_pci = &pci_dev_ops_pci, |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 120 | .scan_bus = &scan_lpc_bus, |
| 121 | }; |
| 122 | |
| 123 | static const unsigned short pci_device_ids[] = { |
| 124 | PCI_DEVICE_ID_INTEL_SPT_LP_PMC, |
V Sowmya | 7c15047 | 2018-01-23 14:44:45 +0530 | [diff] [blame] | 125 | PCI_DEVICE_ID_INTEL_SPT_H_PMC, |
V Sowmya | acc2a48 | 2018-01-23 15:27:23 +0530 | [diff] [blame^] | 126 | PCI_DEVICE_ID_INTEL_KBP_H_PMC, |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 127 | PCI_DEVICE_ID_INTEL_APL_PMC, |
| 128 | PCI_DEVICE_ID_INTEL_GLK_PMC, |
| 129 | 0 |
| 130 | }; |
| 131 | |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 132 | static const struct pci_driver pch_pmc __pci_driver = { |
Subrata Banik | 2153ea5 | 2017-11-22 15:38:19 +0530 | [diff] [blame] | 133 | .ops = &device_ops, |
| 134 | .vendor = PCI_VENDOR_ID_INTEL, |
| 135 | .devices = pci_device_ids, |
| 136 | }; |