Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <string.h> |
Arthur Heymans | 78ab06a | 2021-05-29 06:58:38 +0200 | [diff] [blame] | 5 | #include <cpu/x86/lapic.h> |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 6 | #include <cpu/x86/mp.h> |
| 7 | #include <cpu/intel/em64t101_save_state.h> |
| 8 | #include <cpu/intel/smm_reloc.h> |
| 9 | #include <console/console.h> |
| 10 | #include <smp/node.h> |
| 11 | #include <soc/msr.h> |
| 12 | #include <soc/smmrelocate.h> |
| 13 | |
| 14 | static void fill_in_relocation_params(struct smm_relocation_params *params) |
| 15 | { |
| 16 | uintptr_t tseg_base; |
| 17 | size_t tseg_size; |
| 18 | |
| 19 | smm_region(&tseg_base, &tseg_size); |
| 20 | |
| 21 | if (!IS_ALIGNED(tseg_base, tseg_size)) { |
| 22 | /* |
| 23 | * Note SMRR2 is supported which might support base/size combinations. |
| 24 | * For now it looks like FSP-M always uses aligned base/size, so let's |
| 25 | * not care about that. |
| 26 | */ |
| 27 | printk(BIOS_WARNING, |
| 28 | "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); |
| 29 | return; |
| 30 | } |
| 31 | |
| 32 | /* SMRR has 32-bits of valid address aligned to 4KiB. */ |
| 33 | if (!IS_ALIGNED(tseg_size, 4 * KiB)) { |
| 34 | printk(BIOS_WARNING, |
| 35 | "TSEG size not aligned to the minimum 4KiB! Not setting SMRR\n"); |
| 36 | return; |
| 37 | } |
| 38 | |
| 39 | smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); |
| 40 | |
| 41 | params->smrr_base.lo = tseg_base | MTRR_TYPE_WRBACK; |
| 42 | params->smrr_base.hi = 0; |
| 43 | params->smrr_mask.lo = ~(tseg_size - 1) | MTRR_PHYS_MASK_VALID; |
| 44 | params->smrr_mask.hi = 0; |
| 45 | } |
| 46 | |
| 47 | static void setup_ied_area(struct smm_relocation_params *params) |
| 48 | { |
| 49 | char *ied_base; |
| 50 | |
| 51 | const struct ied_header ied = { |
| 52 | .signature = "INTEL RSVD", |
| 53 | .size = params->ied_size, |
| 54 | .reserved = {0}, |
| 55 | }; |
| 56 | |
| 57 | ied_base = (void *)params->ied_base; |
| 58 | |
| 59 | printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); |
| 60 | printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); |
| 61 | |
| 62 | /* Place IED header at IEDBASE. */ |
| 63 | memcpy(ied_base, &ied, sizeof(ied)); |
| 64 | |
| 65 | assert(params->ied_size > 1 * MiB + 32 * KiB); |
| 66 | |
| 67 | /* Zero out 32KiB at IEDBASE + 1MiB */ |
| 68 | memset(ied_base + 1 * MiB, 0, 32 * KiB); |
| 69 | } |
| 70 | |
| 71 | void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 72 | size_t *smm_save_state_size) |
| 73 | { |
| 74 | fill_in_relocation_params(&smm_reloc_params); |
| 75 | |
| 76 | smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); |
| 77 | |
| 78 | if (smm_reloc_params.ied_size) |
| 79 | setup_ied_area(&smm_reloc_params); |
| 80 | |
| 81 | *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); |
| 82 | } |
| 83 | |
| 84 | static void update_save_state(int cpu, uintptr_t curr_smbase, |
| 85 | uintptr_t staggered_smbase, |
| 86 | struct smm_relocation_params *relo_params) |
| 87 | { |
| 88 | u32 smbase; |
| 89 | u32 iedbase; |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 90 | em64t101_smm_state_save_area_t *save_state; |
| 91 | /* |
| 92 | * The relocated handler runs with all CPUs concurrently. Therefore |
| 93 | * stagger the entry points adjusting SMBASE downwards by save state |
| 94 | * size * CPU num. |
| 95 | */ |
| 96 | smbase = staggered_smbase; |
| 97 | iedbase = relo_params->ied_base; |
| 98 | |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 99 | printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n", |
Arthur Heymans | 78ab06a | 2021-05-29 06:58:38 +0200 | [diff] [blame] | 100 | smbase, iedbase, initial_lapicid()); |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 101 | |
| 102 | save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); |
| 103 | |
| 104 | save_state->smbase = smbase; |
| 105 | save_state->iedbase = iedbase; |
| 106 | } |
| 107 | |
| 108 | /* |
| 109 | * The relocation work is actually performed in SMM context, but the code |
| 110 | * resides in the ramstage module. This occurs by trampolining from the default |
| 111 | * SMRAM entry point to here. |
| 112 | */ |
| 113 | void smm_relocation_handler(int cpu, uintptr_t curr_smbase, |
| 114 | uintptr_t staggered_smbase) |
| 115 | { |
Johnny Lin | 161d090 | 2022-03-29 22:44:47 +0800 | [diff] [blame] | 116 | msr_t mtrr_cap, msr; |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 117 | struct smm_relocation_params *relo_params = &smm_reloc_params; |
| 118 | |
| 119 | printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu); |
| 120 | |
| 121 | /* Make appropriate changes to the save state map. */ |
| 122 | update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); |
| 123 | |
| 124 | /* Write SMRR MSRs based on indicated support. */ |
| 125 | mtrr_cap = rdmsr(MTRR_CAP_MSR); |
Johnny Lin | 161d090 | 2022-03-29 22:44:47 +0800 | [diff] [blame] | 126 | |
| 127 | /* Set Lock bit if supported */ |
| 128 | if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) { |
| 129 | msr = rdmsr(IA32_SMRR_PHYS_MASK); |
| 130 | /* Don't write the same core scope MSR if another thread has locked it, |
| 131 | otherwise system would hang. */ |
| 132 | if (msr.lo & SMRR_PHYS_MASK_LOCK) |
| 133 | return; |
| 134 | relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; |
| 135 | } |
| 136 | |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 137 | if (mtrr_cap.lo & SMRR_SUPPORTED) |
| 138 | write_smrr(relo_params); |
| 139 | } |