Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 2 | |
| 3 | #include <device/device.h> |
| 4 | #include <device/pci.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <fsp/util.h> |
Dinesh Gehlot | 3e86681 | 2023-01-17 05:57:56 +0000 | [diff] [blame] | 7 | #include <gpio.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 8 | #include <intelblocks/acpi.h> |
| 9 | #include <intelblocks/cfg.h> |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 10 | #include <intelblocks/irq.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 11 | #include <intelblocks/itss.h> |
Caveh Jalali | 7eaac6c | 2020-07-24 21:57:10 -0700 | [diff] [blame] | 12 | #include <intelblocks/pcie_rp.h> |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 13 | #include <intelblocks/systemagent.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 14 | #include <intelblocks/xdci.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 15 | #include <soc/intel/common/vbt.h> |
| 16 | #include <soc/itss.h> |
| 17 | #include <soc/pci_devs.h> |
| 18 | #include <soc/ramstage.h> |
| 19 | #include <soc/soc_chip.h> |
| 20 | |
| 21 | #if CONFIG(HAVE_ACPI_TABLES) |
| 22 | const char *soc_acpi_name(const struct device *dev) |
| 23 | { |
| 24 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 25 | return "PCI0"; |
| 26 | |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 27 | if (dev->path.type == DEVICE_PATH_USB) { |
| 28 | switch (dev->path.usb.port_type) { |
| 29 | case 0: |
| 30 | /* Root Hub */ |
| 31 | return "RHUB"; |
| 32 | case 2: |
| 33 | /* USB2 ports */ |
| 34 | switch (dev->path.usb.port_id) { |
| 35 | case 0: return "HS01"; |
| 36 | case 1: return "HS02"; |
| 37 | case 2: return "HS03"; |
| 38 | case 3: return "HS04"; |
| 39 | case 4: return "HS05"; |
| 40 | case 5: return "HS06"; |
| 41 | case 6: return "HS07"; |
| 42 | case 7: return "HS08"; |
| 43 | case 8: return "HS09"; |
| 44 | case 9: return "HS10"; |
Jeremy Soller | d0bf247 | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 45 | /* PCH-H only */ |
| 46 | case 10: return "HS11"; |
| 47 | case 11: return "HS12"; |
| 48 | case 12: return "HS13"; |
| 49 | case 13: return "HS14"; |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 50 | } |
| 51 | break; |
| 52 | case 3: |
| 53 | /* USB3 ports */ |
| 54 | switch (dev->path.usb.port_id) { |
| 55 | case 0: return "SS01"; |
| 56 | case 1: return "SS02"; |
| 57 | case 2: return "SS03"; |
| 58 | case 3: return "SS04"; |
Jeremy Soller | d0bf247 | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 59 | /* PCH-H only */ |
| 60 | case 4: return "SS05"; |
| 61 | case 5: return "SS06"; |
| 62 | case 6: return "SS07"; |
| 63 | case 7: return "SS08"; |
| 64 | case 8: return "SS09"; |
| 65 | case 9: return "SS10"; |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 66 | } |
| 67 | break; |
| 68 | } |
| 69 | return NULL; |
| 70 | } |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 71 | if (dev->path.type != DEVICE_PATH_PCI) |
| 72 | return NULL; |
| 73 | |
| 74 | switch (dev->path.pci.devfn) { |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 75 | case SA_DEVFN_ROOT: return "MCHC"; |
Jeremy Soller | bc071fe | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 76 | case SA_DEVFN_CPU_PCIE: return "PEG0"; |
| 77 | case SA_DEVFN_PEG1: return "PEG1"; |
| 78 | case SA_DEVFN_PEG2: return "PEG2"; |
| 79 | case SA_DEVFN_PEG3: return "PEG3"; |
Matt DeVillier | 1cbdb20 | 2023-10-19 20:31:08 -0500 | [diff] [blame] | 80 | case SA_DEVFN_IGD: return "GFX0"; |
| 81 | case SA_DEVFN_TCSS_XHCI: return "TXHC"; |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 82 | case SA_DEVFN_TCSS_XDCI: return "TXDC"; |
Matt DeVillier | 1cbdb20 | 2023-10-19 20:31:08 -0500 | [diff] [blame] | 83 | case SA_DEVFN_TCSS_DMA0: return "TDM0"; |
| 84 | case SA_DEVFN_TCSS_DMA1: return "TDM1"; |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 85 | case SA_DEVFN_TBT0: return "TRP0"; |
| 86 | case SA_DEVFN_TBT1: return "TRP1"; |
| 87 | case SA_DEVFN_TBT2: return "TRP2"; |
| 88 | case SA_DEVFN_TBT3: return "TRP3"; |
Tim Wawrzynczak | 4b74814 | 2020-06-29 12:34:55 -0600 | [diff] [blame] | 89 | case SA_DEVFN_IPU: return "IPU0"; |
Matt DeVillier | ecf2b42 | 2023-08-31 10:06:00 -0500 | [diff] [blame] | 90 | case SA_DEVFN_GNA: return "GNA"; |
Matt DeVillier | 1cbdb20 | 2023-10-19 20:31:08 -0500 | [diff] [blame] | 91 | case SA_DEVFN_DPTF: return "TCPU"; |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 92 | case PCH_DEVFN_ISH: return "ISHB"; |
| 93 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 94 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 95 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 96 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 97 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 98 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 99 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 100 | case PCH_DEVFN_SATA: return "SATA"; |
| 101 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 102 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 103 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 104 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 105 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 106 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 107 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 108 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 109 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 110 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 111 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 112 | case PCH_DEVFN_PCIE12: return "RP12"; |
Jeremy Soller | 83d795c | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 113 | case PCH_DEVFN_PCIE13: return "RP13"; |
| 114 | case PCH_DEVFN_PCIE14: return "RP14"; |
| 115 | case PCH_DEVFN_PCIE15: return "RP15"; |
| 116 | case PCH_DEVFN_PCIE16: return "RP16"; |
| 117 | case PCH_DEVFN_PCIE17: return "RP17"; |
| 118 | case PCH_DEVFN_PCIE18: return "RP18"; |
| 119 | case PCH_DEVFN_PCIE19: return "RP19"; |
| 120 | case PCH_DEVFN_PCIE20: return "RP20"; |
| 121 | case PCH_DEVFN_PCIE21: return "RP21"; |
| 122 | case PCH_DEVFN_PCIE22: return "RP22"; |
| 123 | case PCH_DEVFN_PCIE23: return "RP23"; |
| 124 | case PCH_DEVFN_PCIE24: return "RP24"; |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 125 | case PCH_DEVFN_PMC: return "PMC"; |
| 126 | case PCH_DEVFN_UART0: return "UAR0"; |
| 127 | case PCH_DEVFN_UART1: return "UAR1"; |
| 128 | case PCH_DEVFN_UART2: return "UAR2"; |
| 129 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 130 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 131 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 132 | case PCH_DEVFN_GSPI3: return "SPI3"; |
Matt DeVillier | 1cbdb20 | 2023-10-19 20:31:08 -0500 | [diff] [blame] | 133 | case PCH_DEVFN_ESPI: return "LPCB"; |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 134 | case PCH_DEVFN_HDA: return "HDAS"; |
| 135 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 136 | case PCH_DEVFN_GBE: return "GLAN"; |
Matt DeVillier | 1cbdb20 | 2023-10-19 20:31:08 -0500 | [diff] [blame] | 137 | case PCH_DEVFN_SRAM: return "SRAM"; |
| 138 | case PCH_DEVFN_SPI: return "FSPI"; |
| 139 | case PCH_DEVFN_CSE: return "HEC1"; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | return NULL; |
| 143 | } |
| 144 | #endif |
| 145 | |
Angel Pons | 73a22ed | 2021-04-05 12:26:51 +0200 | [diff] [blame] | 146 | /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 147 | static void soc_fill_gpio_pm_configuration(void) |
| 148 | { |
| 149 | uint8_t value[TOTAL_GPIO_COMM]; |
| 150 | const config_t *config = config_of_soc(); |
| 151 | |
| 152 | if (config->gpio_override_pm) |
Angel Pons | 0c0d492 | 2021-04-05 13:02:45 +0200 | [diff] [blame] | 153 | memcpy(value, config->gpio_pm, sizeof(value)); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 154 | else |
Angel Pons | 0c0d492 | 2021-04-05 13:02:45 +0200 | [diff] [blame] | 155 | memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 156 | |
| 157 | gpio_pm_configure(value, TOTAL_GPIO_COMM); |
| 158 | } |
| 159 | |
| 160 | void soc_init_pre_device(void *chip_info) |
| 161 | { |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 162 | /* Perform silicon specific init. */ |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 163 | fsp_silicon_init(); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 164 | |
| 165 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 166 | fsp_display_fvi_version_hob(); |
| 167 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 168 | soc_fill_gpio_pm_configuration(); |
Caveh Jalali | 7eaac6c | 2020-07-24 21:57:10 -0700 | [diff] [blame] | 169 | |
| 170 | /* Swap enabled PCI ports in device tree if needed. */ |
Michael Niewöhner | 9f0285b | 2022-01-09 02:20:17 +0100 | [diff] [blame] | 171 | const struct pcie_rp_group *pch_rp_groups = soc_get_pch_rp_groups(); |
| 172 | pcie_rp_update_devicetree(pch_rp_groups); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 173 | } |
| 174 | |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 175 | static void cpu_fill_ssdt(const struct device *dev) |
| 176 | { |
| 177 | if (!generate_pin_irq_map()) |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 178 | printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n"); |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 179 | |
| 180 | generate_cpu_entries(dev); |
| 181 | } |
| 182 | |
| 183 | static void cpu_set_north_irqs(struct device *dev) |
| 184 | { |
| 185 | irq_program_non_pch(); |
| 186 | } |
| 187 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 188 | static struct device_operations pci_domain_ops = { |
| 189 | .read_resources = &pci_domain_read_resources, |
| 190 | .set_resources = &pci_domain_set_resources, |
Arthur Heymans | 0b0113f | 2023-08-31 17:09:28 +0200 | [diff] [blame] | 191 | .scan_bus = &pci_host_bridge_scan_bus, |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 192 | #if CONFIG(HAVE_ACPI_TABLES) |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 193 | .acpi_name = &soc_acpi_name, |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 194 | .acpi_fill_ssdt = ssdt_set_above_4g_pci, |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 195 | #endif |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 199 | .read_resources = noop_read_resources, |
| 200 | .set_resources = noop_set_resources, |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 201 | .enable_resources = cpu_set_north_irqs, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 202 | #if CONFIG(HAVE_ACPI_TABLES) |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 203 | .acpi_fill_ssdt = cpu_fill_ssdt, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 204 | #endif |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 205 | }; |
| 206 | |
| 207 | static void soc_enable(struct device *dev) |
| 208 | { |
Tim Wawrzynczak | 6d20d0c | 2020-05-13 17:00:33 -0600 | [diff] [blame] | 209 | /* |
| 210 | * Set the operations if it is a special bus type or a hidden PCI |
| 211 | * device. |
| 212 | */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 213 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 214 | dev->ops = &pci_domain_ops; |
| 215 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 216 | dev->ops = &cpu_bus_ops; |
Tim Wawrzynczak | 6d20d0c | 2020-05-13 17:00:33 -0600 | [diff] [blame] | 217 | else if (dev->path.type == DEVICE_PATH_PCI && |
| 218 | dev->path.pci.devfn == PCH_DEVFN_PMC) |
| 219 | dev->ops = &pmc_ops; |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 220 | else if (dev->path.type == DEVICE_PATH_GPIO) |
| 221 | block_gpio_enable(dev); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | struct chip_operations soc_intel_tigerlake_ops = { |
| 225 | CHIP_NAME("Intel Tigerlake") |
| 226 | .enable_dev = &soc_enable, |
| 227 | .init = &soc_init_pre_device, |
| 228 | }; |